337 lines
11 KiB
C
337 lines
11 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-23 Mr.Tiger first version
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* 2021-11-04 Sherman ADD complete_event
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* 2022-12-7 Vandoul ADD sci spi
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*/
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/**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
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#include "drv_sci_spi.h"
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#ifdef RT_USING_SPI
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//#define DRV_DEBUG
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#define DBG_TAG "drv.scispi"
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#ifdef DRV_DEBUG
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#define DBG_LVL DBG_LOG
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#else
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#define DBG_LVL DBG_INFO
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#endif /* DRV_DEBUG */
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#include <rtdbg.h>
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#define RA_SCI_SPI0_EVENT 0x0001
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#define RA_SCI_SPI1_EVENT 0x0002
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#define RA_SCI_SPI2_EVENT 0x0004
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#define RA_SCI_SPI3_EVENT 0x0008
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#define RA_SCI_SPI4_EVENT 0x0010
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#define RA_SCI_SPI5_EVENT 0x0020
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#define RA_SCI_SPI6_EVENT 0x0040
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#define RA_SCI_SPI7_EVENT 0x0080
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#define RA_SCI_SPI8_EVENT 0x0100
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#define RA_SCI_SPI9_EVENT 0x0200
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static struct rt_event complete_event = {0};
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static struct ra_sci_spi_handle spi_handle[] =
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{
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#ifdef BSP_USING_SCI_SPI0
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{.bus_name = "scpi0", .spi_ctrl_t = &g_sci_spi0_ctrl, .spi_cfg_t = &g_sci_spi0_cfg,},
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#endif
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#ifdef BSP_USING_SCI_SPI1
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{.bus_name = "scpi1", .spi_ctrl_t = &g_sci_spi1_ctrl, .spi_cfg_t = &g_sci_spi1_cfg,},
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#endif
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#ifdef BSP_USING_SCI_SPI2
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{.bus_name = "scpi2", .spi_ctrl_t = &g_sci_spi2_ctrl, .spi_cfg_t = &g_sci_spi2_cfg,},
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#endif
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#ifdef BSP_USING_SCI_SPI3
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{.bus_name = "scpi3", .spi_ctrl_t = &g_sci_spi3_ctrl, .spi_cfg_t = &g_sci_spi3_cfg,},
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#endif
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#ifdef BSP_USING_SCI_SPI4
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{.bus_name = "scpi4", .spi_ctrl_t = &g_sci_spi4_ctrl, .spi_cfg_t = &g_sci_spi4_cfg,},
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#endif
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#ifdef BSP_USING_SCI_SPI5
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{.bus_name = "scpi5", .spi_ctrl_t = &g_sci_spi5_ctrl, .spi_cfg_t = &g_sci_spi5_cfg,},
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#endif
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#ifdef BSP_USING_SCI_SPI6
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{.bus_name = "scpi6", .spi_ctrl_t = &g_sci_spi6_ctrl, .spi_cfg_t = &g_sci_spi6_cfg,},
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#endif
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#ifdef BSP_USING_SCI_SPI7
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{.bus_name = "scpi7", .spi_ctrl_t = &g_sci_spi7_ctrl, .spi_cfg_t = &g_sci_spi7_cfg,},
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#endif
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#ifdef BSP_USING_SCI_SPI8
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{.bus_name = "scpi8", .spi_ctrl_t = &g_sci_spi8_ctrl, .spi_cfg_t = &g_sci_spi8_cfg,},
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#endif
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#ifdef BSP_USING_SCI_SPI9
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{.bus_name = "scpi9", .spi_ctrl_t = &g_sci_spi9_ctrl, .spi_cfg_t = &g_sci_spi9_cfg,},
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#endif
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};
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static struct ra_sci_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0};
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#define SCI_SPIx_CALLBACK(n) \
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void sci_spi##n##_callback(spi_callback_args_t *p_args) \
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{ \
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rt_interrupt_enter(); \
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if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event) \
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{ \
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rt_event_send(&complete_event, RA_SCI_SPI##n##_EVENT); \
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} \
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rt_interrupt_leave(); \
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}
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SCI_SPIx_CALLBACK(0);
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SCI_SPIx_CALLBACK(1);
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SCI_SPIx_CALLBACK(2);
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SCI_SPIx_CALLBACK(3);
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SCI_SPIx_CALLBACK(4);
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SCI_SPIx_CALLBACK(5);
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SCI_SPIx_CALLBACK(6);
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SCI_SPIx_CALLBACK(7);
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SCI_SPIx_CALLBACK(8);
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SCI_SPIx_CALLBACK(9);
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#define SCI_SPIx_EVENT_RECV(n) \
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rt_event_recv(event, \
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RA_SCI_SPI##n##_EVENT, \
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RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, \
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RT_WAITING_FOREVER, \
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&recved);
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static rt_err_t ra_wait_complete(rt_event_t event, const char bus_name[RT_NAME_MAX])
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{
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rt_uint32_t recved = 0x00;
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switch (bus_name[6])
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{
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case '0':
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return SCI_SPIx_EVENT_RECV(0);
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case '1':
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return SCI_SPIx_EVENT_RECV(1);
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case '2':
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return SCI_SPIx_EVENT_RECV(2);
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case '3':
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return SCI_SPIx_EVENT_RECV(3);
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case '4':
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return SCI_SPIx_EVENT_RECV(4);
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case '5':
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return SCI_SPIx_EVENT_RECV(5);
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case '6':
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return SCI_SPIx_EVENT_RECV(6);
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case '7':
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return SCI_SPIx_EVENT_RECV(7);
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case '8':
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return SCI_SPIx_EVENT_RECV(8);
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case '9':
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return SCI_SPIx_EVENT_RECV(9);
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}
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return -RT_EINVAL;
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}
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static spi_bit_width_t ra_width_shift(rt_uint8_t data_width)
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{
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spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS;
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if(data_width == 1)
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bit_width = SPI_BIT_WIDTH_8_BITS;
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else if(data_width == 2)
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bit_width = SPI_BIT_WIDTH_16_BITS;
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else if(data_width == 4)
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bit_width = SPI_BIT_WIDTH_32_BITS;
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return bit_width;
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}
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static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
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{
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RT_ASSERT(device != NULL);
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RT_ASSERT(device->parent.user_data != NULL);
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RT_ASSERT(send_buf != NULL);
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RT_ASSERT(len > 0);
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rt_err_t err = RT_EOK;
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struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
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spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
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/**< send msessage */
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err = R_SCI_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, bit_width);
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if (RT_EOK != err)
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{
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LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
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return -RT_ERROR;
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}
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/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
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ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
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return len;
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}
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static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len)
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{
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RT_ASSERT(device != NULL);
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RT_ASSERT(device->parent.user_data != NULL);
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RT_ASSERT(recv_buf != NULL);
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RT_ASSERT(len > 0);
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rt_err_t err = RT_EOK;
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struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
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spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
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/**< receive message */
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err = R_SCI_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, bit_width);
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if (RT_EOK != err)
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{
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LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
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return -RT_ERROR;
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}
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/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
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ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
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return len;
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}
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static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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RT_ASSERT(device != NULL);
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RT_ASSERT(message != NULL);
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RT_ASSERT(message->length > 0);
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rt_err_t err = RT_EOK;
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struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
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spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
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/**< write and receive message */
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err = R_SCI_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, bit_width);
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if (RT_EOK != err)
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{
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LOG_E("%s write and read failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
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return -RT_ERROR;
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}
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/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
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ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
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return message->length;
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}
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/**< init spi TODO : MSB does not support modification */
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static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration)
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{
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RT_ASSERT(device != NULL);
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RT_ASSERT(configuration != NULL);
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rt_err_t err = RT_EOK;
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struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
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spi_dev->cs_pin = (rt_uint32_t)device->parent.user_data;
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/**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/
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rt_uint8_t data_width = configuration->data_width / 8;
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RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4);
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configuration->data_width = configuration->data_width / 8;
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spi_dev->rt_spi_cfg_t = configuration;
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sci_spi_extended_cfg_t *spi_cfg = (sci_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
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/**< Configure Select Line */
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rt_pin_write(spi_dev->cs_pin, PIN_HIGH);
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/**< config bitrate */
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R_SCI_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->clk_div, false);
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/**< init */
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err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
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/* handle error */
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if(err == FSP_ERR_IN_USE) {
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R_SCI_SPI_Close((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t);
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err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
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}
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if (RT_EOK != err)
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{
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LOG_E("%s init failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
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return -RT_ERROR;
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}
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return RT_EOK;
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}
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static rt_uint32_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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rt_err_t err = RT_EOK;
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struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
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spi_dev->cs_pin = (rt_uint32_t)device->parent.user_data;
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if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS))
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{
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if (device->config.mode & RT_SPI_CS_HIGH)
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rt_pin_write(spi_dev->cs_pin, PIN_HIGH);
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else
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rt_pin_write(spi_dev->cs_pin, PIN_LOW);
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}
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if (message->length > 0)
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{
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if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
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{
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/**< receive message */
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err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length);
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}
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else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
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{
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/**< send message */
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err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length);
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}
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else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
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{
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/**< send and receive message */
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err = ra_write_read_message(device, message);
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}
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}
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if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
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{
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if (device->config.mode & RT_SPI_CS_HIGH)
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rt_pin_write(spi_dev->cs_pin, PIN_LOW);
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else
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rt_pin_write(spi_dev->cs_pin, PIN_HIGH);
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}
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return err;
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}
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static const struct rt_spi_ops ra_spi_ops =
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{
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.configure = ra_hw_spi_configure,
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.xfer = ra_spixfer,
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};
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int ra_hw_sci_spi_init(void)
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{
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for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
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{
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spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index];
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/**< register spi bus */
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rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops);
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if (RT_EOK != err)
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{
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LOG_E("%s bus register failed. %d", spi_config[spi_index].ra_spi_handle_t->bus_name, err);
|
||
|
|
return -RT_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (RT_EOK != rt_event_init(&complete_event, "ra_scispi", RT_IPC_FLAG_PRIO))
|
||
|
|
{
|
||
|
|
LOG_E("SPI transfer event init fail!");
|
||
|
|
return -RT_ERROR;
|
||
|
|
}
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(ra_hw_sci_spi_init);
|
||
|
|
#endif /* RT_USING_SPI */
|