2013-01-08 21:05:02 +08:00
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#ifndef __JZ4755_H__
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#define __JZ4755_H__
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#include "jz47xx.h"
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#define WDT_BASE 0xB0002000
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#define OST_BASE 0xB00020e0
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/* Watchdog */
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#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
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#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
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#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
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#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
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/* OS Timer */
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#define OST_DR __REG32(OST_BASE + 0x00) /* OS Timer Data Register */
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#define OST_CNT __REG32(OST_BASE + 0x08) /* OS Timer Counter Register */
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#define OST_CSR __REG16(OST_BASE + 0x0C) /* OS Timer Control Register */
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/* OST Register Definitions */
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#define OST_TCSR_EXT_EN ( 0x1 << 2)
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#define OST_TCSR_RTC_EN ( 0x1 << 1)
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#define OST_TCSR_PCLK_EN ( 0x1 << 0)
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/* Clock Gate Register Definitions */
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#define CPM_CLKGR_AUX_CPU ( 1 << 24 )
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#define CPM_CLKGR_AHB1 ( 1 << 23 )
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#define CPM_CLKGR_IDCT ( 1 << 22 )
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#define CPM_CLKGR_DB ( 1 << 21 )
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#define CPM_CLKGR_ME ( 1 << 20 )
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#define CPM_CLKGR_MC ( 1 << 19 )
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#define CPM_CLKGR_TVE ( 1 << 18 )
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#define CPM_CLKGR_TSSI ( 1 << 17 )
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#define CPM_CLKGR_MSC1 ( 1 << 16 )
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#define CPM_CLKGR_UART2 ( 1 << 15 )
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#define CPM_CLKGR_UART1 ( 1 << 14 )
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#define CPM_CLKGR_IPU ( 1 << 13 )
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#define CPM_CLKGR_DMAC ( 1 << 12 )
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#define CPM_CLKGR_BCH ( 1 << 11 )
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#define CPM_CLKGR_UDC ( 1 << 10 )
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#define CPM_CLKGR_LCD ( 1 << 9 )
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#define CPM_CLKGR_CIM ( 1 << 8 )
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#define CPM_CLKGR_SADC ( 1 << 7 )
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#define CPM_CLKGR_MSC0 ( 1 << 6 )
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#define CPM_CLKGR_AIC ( 1 << 5 )
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#define CPM_CLKGR_SSI1 ( 1 << 4 )
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#define CPM_CLKGR_I2C ( 1 << 3 )
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#define CPM_CLKGR_RTC ( 1 << 2 )
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#define CPM_CLKGR_TCU ( 1 << 1 )
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#define CPM_CLKGR_UART0 ( 1 << 0 )
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/* Interrupt Definitions */
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#define IRQ_ETH 0
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#define IRQ_SFT 4
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#define IRQ_I2C 5
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#define IRQ_RTC 6
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#define IRQ_UART2 7
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#define IRQ_UART1 8
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#define IRQ_UART0 9
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#define IRQ_AIC 10
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#define IRQ_GPIO5 11
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#define IRQ_GPIO4 12
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#define IRQ_GPIO3 13
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#define IRQ_GPIO2 14
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#define IRQ_GPIO1 15
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#define IRQ_GPIO0 16
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#define IRQ_BCH 17
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#define IRQ_SADC 18
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#define IRQ_CIM 19
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#define IRQ_TSSI 20
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#define IRQ_TCU2 21
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#define IRQ_TCU1 22
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#define IRQ_TCU0 23
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#define IRQ_MSC1 24
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#define IRQ_MSC0 25
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#define IRQ_SSI 26
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#define IRQ_UDC 27
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#define IRQ_DMA1 28 /* Used for DMA channel 4-7 */
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#define IRQ_DMA0 29 /* Used for DMA channel 0-3 */
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#define IRQ_IPU 30
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#define IRQ_LCD 31
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#endif
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