2013-01-08 22:40:58 +08:00
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;/*---------------------------------------------------------------------------------------------------------*/
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;/* */
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;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */
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;/* */
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;/*---------------------------------------------------------------------------------------------------------*/
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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CLK_BA_base EQU 0x50000200
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PWRCON EQU 0x00
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AHBCLK EQU 0x04
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APBCLK EQU 0x08
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CLKSEL0 EQU 0x10
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CLKSEL1 EQU 0x14
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CLKDIV EQU 0x18
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PLLCON EQU 0x20
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TEST_S EQU 0x30
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CLK_BA_APBCLK EQU 0x50000208
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;// Define clock enable registers
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ADC_COMP_CLK EQU 0x50000208
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ADC_enable EQU 0x10000000
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COMP_enable EQU 0x40000000
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PDMA_CLK EQU 0x50000204
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PDMA_enable EQU 0x00000003
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;; bit 0 CPU_EN
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;; bit 1 PDMA_EN
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;// Define COMP registers base
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COMP_base EQU 0x400D0000
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CMP1CR EQU 0x00
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CMP2CR EQU 0x04
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CMPSR EQU 0x08
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;// Define ADC registers base
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ADC_base EQU 0x400E0000
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ADDR0 EQU 0x00
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ADDR1 EQU 0x04
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ADDR2 EQU 0x08
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ADDR3 EQU 0x0c
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ADDR4 EQU 0x10
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ADDR5 EQU 0x14
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ADDR6 EQU 0x18
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ADDR7 EQU 0x1c
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ADCR EQU 0x20
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ADCHER EQU 0x24
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ADCMPR0 EQU 0x28
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ADCMPR1 EQU 0x2c
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ADSR EQU 0x30
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ADCALR EQU 0x34
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ADCFCR EQU 0x38
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ADCALD EQU 0x3c
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;// Pattern Table
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pattern_55555555 EQU 0x55555555
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pattern_aaaaaaaa EQU 0xaaaaaaaa
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pattern_00005555 EQU 0x00005555
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pattern_0000aaaa EQU 0x0000aaaa
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pattern_05550515 EQU 0x05550515
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pattern_0aaa0a2a EQU 0x0aaa0a2a
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;// Define PDMA regsiter base
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PDMA_BA_ch0_base EQU 0x50008000
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PDMA_BA_ch1_base EQU 0x50008100
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PDMA_BA_ch2_base EQU 0x50008200
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PDMA_BA_ch3_base EQU 0x50008300
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PDMA_BA_ch4_base EQU 0x50008400
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PDMA_BA_ch5_base EQU 0x50008500
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PDMA_BA_ch6_base EQU 0x50008600
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PDMA_BA_ch7_base EQU 0x50008700
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PDMA_BA_GCR EQU 0x50008F00
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PDMA_BA_GCR_base EQU 0x50008F00
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PDMA_GCRCSR EQU 0X00
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PDMA_PDSSR2 EQU 0X04
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PDMA_PDSSR1 EQU 0X08 ;; PDMA channel select 0x77000000
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PDMA_GCRISR EQU 0X0C
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PDMA_GLOBAL_enable EQU 0x0000FF00
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PDMA_CSR EQU 0X00
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PDMA_SAR EQU 0X04
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PDMA_DAR EQU 0X08
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PDMA_BCR EQU 0X0C
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PDMA_CSAR EQU 0X14
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PDMA_CDAR EQU 0X18
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PDMA_CBSR EQU 0X1C
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PDMA_IER EQU 0X20
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PDMA_ISR EQU 0X24
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PDMA_CTCSR EQU 0X28
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PDMA_SASOCR EQU 0X2C
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PDMA_DASOCR EQU 0X30
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PDMA_SBUF0 EQU 0X80
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PDMA_SBUF1 EQU 0X84
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PDMA_SBUF2 EQU 0X88
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PDMA_SBUF3 EQU 0X8C
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;// Define VIC control register
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VIC_base EQU 0xFFFF0000
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VIC_SCR15 EQU 0x003c
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VIC_SVR15 EQU 0x00bc
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VIC_SCR16 EQU 0x0040
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VIC_SVR16 EQU 0x00c0
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VIC_SCR30 EQU 0x0078
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VIC_SVR30 EQU 0x00f8
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VIC_MECR EQU 0x0318
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VIC_MDCR EQU 0x031c
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VIC_EOSCR EQU 0x0130
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;//==================================
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INT_BA_base EQU 0x50000300
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;// Parameter table
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ADC_PDMA_CFG EQU 0x00002980
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ADC_PDMA_DST EQU 0xC0000000
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ADC_PDMA_SRC EQU 0xE0024200
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ADC_PDMA_TCBL EQU 0x00030008
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;//==================================
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GPIO_base EQU 0x50004000
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GPIOB_PMD EQU 0x0040
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GPIOB_OFFD EQU 0x0044
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GPIOB_DOUT EQU 0x0048
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GPIOB_DMASK EQU 0x004C
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GPIOB_PIN EQU 0x0050
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GPIOB_DBEN EQU 0x0054
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GPIOB_IMD EQU 0x0058
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GPIOB_IEN EQU 0x005C
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GPIOB_ISRC EQU 0x0060
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;//==================================
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GCR_base EQU 0x50000000
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GPB_MFP EQU 0x0034
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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; maximum of 32 External Interrupts are possible
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DCD BOD_IRQHandler
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DCD WDT_IRQHandler
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DCD EINT0_IRQHandler
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DCD EINT1_IRQHandler
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DCD GPAB_IRQHandler
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DCD GPCDE_IRQHandler
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DCD PWMA_IRQHandler
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DCD PWMB_IRQHandler
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DCD TMR0_IRQHandler
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DCD TMR1_IRQHandler
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DCD TMR2_IRQHandler
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DCD TMR3_IRQHandler
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DCD UART0_IRQHandler
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DCD UART1_IRQHandler
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DCD SPI0_IRQHandler
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DCD SPI1_IRQHandler
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DCD SPI2_IRQHandler
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DCD SPI3_IRQHandler
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DCD I2C0_IRQHandler
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DCD I2C1_IRQHandler
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DCD CAN0_IRQHandler
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DCD CAN1_IRQHandler
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DCD Default_Handler
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DCD USBD_IRQHandler
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DCD PS2_IRQHandler
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DCD ACMP_IRQHandler
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DCD PDMA_IRQHandler
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DCD Default_Handler
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DCD PWRWU_IRQHandler
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DCD ADC_IRQHandler
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DCD Default_Handler
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DCD RTC_IRQHandler
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AREA |.text|, CODE, READONLY
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; Reset Handler
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ENTRY
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __main
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT BOD_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT EINT0_IRQHandler [WEAK]
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EXPORT EINT1_IRQHandler [WEAK]
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EXPORT GPAB_IRQHandler [WEAK]
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EXPORT GPCDE_IRQHandler [WEAK]
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EXPORT PWMA_IRQHandler [WEAK]
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EXPORT PWMB_IRQHandler [WEAK]
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EXPORT TMR0_IRQHandler [WEAK]
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EXPORT TMR1_IRQHandler [WEAK]
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EXPORT TMR2_IRQHandler [WEAK]
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EXPORT TMR3_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT SPI3_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT CAN0_IRQHandler [WEAK]
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EXPORT CAN1_IRQHandler [WEAK]
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EXPORT USBD_IRQHandler [WEAK]
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EXPORT PS2_IRQHandler [WEAK]
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EXPORT ACMP_IRQHandler [WEAK]
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EXPORT PDMA_IRQHandler [WEAK]
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EXPORT PWRWU_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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BOD_IRQHandler
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WDT_IRQHandler
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EINT0_IRQHandler
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EINT1_IRQHandler
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GPAB_IRQHandler
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GPCDE_IRQHandler
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PWMA_IRQHandler
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PWMB_IRQHandler
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TMR0_IRQHandler
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TMR1_IRQHandler
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TMR2_IRQHandler
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TMR3_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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SPI0_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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SPI3_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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CAN0_IRQHandler
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CAN1_IRQHandler
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USBD_IRQHandler
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PS2_IRQHandler
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ACMP_IRQHandler
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PDMA_IRQHandler
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PWRWU_IRQHandler
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ADC_IRQHandler
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RTC_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, = (Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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