487 lines
12 KiB
C
487 lines
12 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-09-10 MXH the first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#ifdef BSP_USING_HWTIMER
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#define DBG_TAG "TIM"
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#define DBG_LVL DBG_LOG
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#include <rtdbg.h>
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#include "drv_hwtimer.h"
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#include "board.h"
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#ifdef RT_USING_HWTIMER
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enum
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{
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#ifdef BSP_USING_TIM1
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TIM1_INDEX,
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#endif
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#ifdef BSP_USING_TIM2
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TIM2_INDEX,
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#endif
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#ifdef BSP_USING_TIM3
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TIM3_INDEX,
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#endif
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#ifdef BSP_USING_TIM4
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TIM4_INDEX,
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#endif
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#ifdef BSP_USING_TIM5
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TIM5_INDEX,
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#endif
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#ifdef BSP_USING_TIM6
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TIM6_INDEX,
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#endif
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#ifdef BSP_USING_TIM7
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TIM7_INDEX,
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#endif
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#ifdef BSP_USING_TIM8
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TIM8_INDEX,
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#endif
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#ifdef BSP_USING_TIM9
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TIM9_INDEX,
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#endif
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#ifdef BSP_USING_TIM10
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TIM10_INDEX,
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#endif
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};
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static struct ch32_hwtimer ch32_hwtimer_obj[] =
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{
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#ifdef BSP_USING_TIM1
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TIM1_CONFIG,
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#endif
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#ifdef BSP_USING_TIM2
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TIM2_CONFIG,
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#endif
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#ifdef BSP_USING_TIM3
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TIM3_CONFIG,
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#endif
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#ifdef BSP_USING_TIM4
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TIM4_CONFIG,
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#endif
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#ifdef BSP_USING_TIM5
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TIM5_CONFIG,
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#endif
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#ifdef BSP_USING_TIM6
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TIM6_CONFIG,
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#endif
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#ifdef BSP_USING_TIM7
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TIM7_CONFIG,
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#endif
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#ifdef BSP_USING_TIM8
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TIM8_CONFIG,
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#endif
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#ifdef BSP_USING_TIM9
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TIM9_CONFIG,
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#endif
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#ifdef BSP_USING_TIM10
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TIM10_CONFIG,
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#endif
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};
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/* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
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void ch32_get_pclk_doubler(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
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{
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RT_ASSERT(pclk1_doubler != RT_NULL);
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RT_ASSERT(pclk2_doubler != RT_NULL);
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*pclk1_doubler = 1;
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*pclk2_doubler = 1;
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if((RCC->CFGR0 & RCC_PPRE1) == RCC_PPRE1_DIV1)
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{
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*pclk1_doubler = 1;
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}
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else
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{
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*pclk1_doubler = 2;
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}
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if((RCC->CFGR0 & RCC_PPRE2) == RCC_PPRE2_DIV1)
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{
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*pclk2_doubler = 1;
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}
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else
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{
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*pclk2_doubler = 2;
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}
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}
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static void ch32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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RT_ASSERT(timer != RT_NULL);
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TIM_HandleTypeDef *tim = RT_NULL;
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RCC_ClocksTypeDef RCC_ClockStruct;
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NVIC_InitTypeDef NVIC_InitStruct;
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struct ch32_hwtimer *tim_device = RT_NULL;
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rt_uint32_t prescaler_value = 0;
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rt_uint32_t pclk1_doubler, pclk2_doubler;
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RCC_GetClocksFreq(&RCC_ClockStruct);
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ch32_get_pclk_doubler(&pclk1_doubler, &pclk2_doubler);
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if(state)
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{
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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tim_device = (struct ch32_hwtimer *)timer;
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if(tim->instance == TIM1 || tim->instance == TIM8 ||
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tim->instance == TIM9 || tim->instance == TIM10)
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{
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RCC_APB2PeriphClockCmd(tim->rcc, ENABLE);
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prescaler_value = (RCC_ClockStruct.PCLK2_Frequency * pclk2_doubler / 10000) - 1;
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}
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else
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{
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RCC_APB1PeriphClockCmd(tim->rcc, ENABLE);
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prescaler_value = (RCC_ClockStruct.PCLK1_Frequency * pclk1_doubler / 10000) - 1;
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}
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tim->init.TIM_Prescaler = prescaler_value;
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tim->init.TIM_ClockDivision = TIM_CKD_DIV1;
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tim->init.TIM_Period = 10000 - 1;
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tim->init.TIM_RepetitionCounter = 0;
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if(timer->info->cntmode == HWTIMER_CNTMODE_UP)
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{
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tim->init.TIM_CounterMode = TIM_CounterMode_Up;
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}
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else
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{
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tim->init.TIM_CounterMode = TIM_CounterMode_Down;
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}
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/* TIM6 and TIM7 only support counter up mode */
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if(tim->instance == TIM6 || tim->instance == TIM7)
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{
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tim->init.TIM_CounterMode = TIM_CounterMode_Up;
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}
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TIM_TimeBaseInit(tim->instance, &tim->init);
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NVIC_InitStruct.NVIC_IRQChannel = tim_device->irqn;
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NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStruct);
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TIM_ClearITPendingBit(tim->instance, TIM_IT_Update);
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TIM_ITConfig(tim->instance, TIM_IT_Update, ENABLE);
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}
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}
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static rt_err_t ch32_hwtimer_start(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
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{
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RT_ASSERT(timer != RT_NULL);
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TIM_HandleTypeDef *tim = RT_NULL;
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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/* set tim cnt */
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tim->instance->CNT = 0;
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/* set tim arr */
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tim->instance->ATRLR = cnt - 1;
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tim->init.TIM_Period = cnt - 1;
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if (mode == HWTIMER_MODE_ONESHOT)
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{
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/* set timer to single mode */
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tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
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tim->instance->CTLR1 |= TIM_OPMode_Single;
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}
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else
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{
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tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
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tim->instance->CTLR1 |= TIM_OPMode_Repetitive;
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}
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/* start timer */
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TIM_Cmd(tim->instance, ENABLE);
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return RT_EOK;
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}
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static void ch32_hwtimer_stop(struct rt_hwtimer_device *timer)
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{
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RT_ASSERT(timer != RT_NULL);
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TIM_HandleTypeDef *tim = RT_NULL;
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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/* stop timer */
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TIM_Cmd(tim->instance, DISABLE);
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/* set tim cnt */
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tim->instance->CNT = 0;
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}
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static rt_uint32_t ch32_hwtimer_count_get(struct rt_hwtimer_device *timer)
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{
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RT_ASSERT(timer != RT_NULL);
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TIM_HandleTypeDef *tim = RT_NULL;
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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return tim->instance->CNT;
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}
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static rt_err_t ch32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args)
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{
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RT_ASSERT(timer != RT_NULL);
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RT_ASSERT(args != RT_NULL);
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TIM_HandleTypeDef *tim = RT_NULL;
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rt_err_t result = RT_EOK;
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rt_uint32_t pclk1_doubler, pclk2_doubler;
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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rt_uint32_t freq;
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rt_uint16_t val;
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RCC_ClocksTypeDef RCC_ClockStruct;
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/* set timer frequence */
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freq = *((rt_uint32_t *)args);
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ch32_get_pclk_doubler(&pclk1_doubler, &pclk2_doubler);
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RCC_GetClocksFreq(&RCC_ClockStruct);
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if(tim->instance == TIM1 || tim->instance == TIM8 ||
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tim->instance == TIM9 || tim->instance == TIM10)
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{
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val = RCC_ClockStruct.PCLK2_Frequency * pclk2_doubler / freq;
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}
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else
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{
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val = RCC_ClockStruct.PCLK1_Frequency * pclk1_doubler / freq;
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}
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/* Update frequency value */
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TIM_PrescalerConfig(tim->instance, val - 1, TIM_PSCReloadMode_Immediate);
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result = RT_EOK;
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break;
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}
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case HWTIMER_CTRL_MODE_SET:
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{
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if (*(rt_hwtimer_mode_t *)args == HWTIMER_MODE_ONESHOT)
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{
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/* set timer to single mode */
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tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
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tim->instance->CTLR1 |= TIM_OPMode_Single;
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}
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else
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{
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tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
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tim->instance->CTLR1 |= TIM_OPMode_Repetitive;
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}
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break;
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}
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case HWTIMER_CTRL_INFO_GET:
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{
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*(rt_hwtimer_mode_t *)args = tim->instance->CNT;
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break;
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}
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case HWTIMER_CTRL_STOP:
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{
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ch32_hwtimer_stop(timer);
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break;
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}
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default:
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{
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result = -RT_EINVAL;
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break;
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}
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}
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return result;
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}
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static const struct rt_hwtimer_info ch32_hwtimer_info = TIM_DEV_INFO_CONFIG;
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static const struct rt_hwtimer_ops ch32_hwtimer_ops =
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{
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ch32_hwtimer_init,
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ch32_hwtimer_start,
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ch32_hwtimer_stop,
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ch32_hwtimer_count_get,
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ch32_hwtimer_control
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};
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static void ch32_hwtimer_isr(struct rt_hwtimer_device *device)
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{
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RT_ASSERT(device != RT_NULL);
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struct ch32_hwtimer *hwtimer = RT_NULL;
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hwtimer = rt_container_of(device, struct ch32_hwtimer, device);
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if(TIM_GetITStatus(hwtimer->handle.instance, TIM_IT_Update) != RESET)
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{
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rt_device_hwtimer_isr(device);
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TIM_ClearITPendingBit(hwtimer->handle.instance, TIM_IT_Update);
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}
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}
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#ifdef BSP_USING_TIM1
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void TIM1_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void TIM1_UP_IRQHandler(void)
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{
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GET_INT_SP();
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rt_interrupt_enter();
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ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM1_INDEX].device));
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rt_interrupt_leave();
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FREE_INT_SP();
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}
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#endif /* BSP_USING_TIM1 */
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#ifdef BSP_USING_TIM2
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void TIM2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void TIM2_IRQHandler(void)
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{
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GET_INT_SP();
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rt_interrupt_enter();
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ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM2_INDEX].device));
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rt_interrupt_leave();
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FREE_INT_SP();
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}
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#endif /* BSP_USING_TIM2 */
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#ifdef BSP_USING_TIM3
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void TIM3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void TIM3_IRQHandler(void)
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{
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GET_INT_SP();
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rt_interrupt_enter();
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ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM3_INDEX].device));
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rt_interrupt_leave();
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FREE_INT_SP();
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}
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#endif /* BSP_USING_TIM3 */
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#ifdef BSP_USING_TIM4
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void TIM4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
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void TIM4_IRQHandler(void)
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{
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GET_INT_SP();
|
||
|
|
rt_interrupt_enter();
|
||
|
|
ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM4_INDEX].device));
|
||
|
|
rt_interrupt_leave();
|
||
|
|
FREE_INT_SP();
|
||
|
|
}
|
||
|
|
#endif /* BSP_USING_TIM4 */
|
||
|
|
|
||
|
|
#ifdef BSP_USING_TIM5
|
||
|
|
void TIM5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||
|
|
void TIM5_IRQHandler(void)
|
||
|
|
{
|
||
|
|
GET_INT_SP();
|
||
|
|
rt_interrupt_enter();
|
||
|
|
ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM5_INDEX].device));
|
||
|
|
rt_interrupt_leave();
|
||
|
|
FREE_INT_SP();
|
||
|
|
}
|
||
|
|
#endif /* BSP_USING_TIM5 */
|
||
|
|
|
||
|
|
#ifdef BSP_USING_TIM6
|
||
|
|
void TIM6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||
|
|
void TIM6_IRQHandler(void)
|
||
|
|
{
|
||
|
|
GET_INT_SP();
|
||
|
|
rt_interrupt_enter();
|
||
|
|
ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM6_INDEX].device));
|
||
|
|
rt_interrupt_leave();
|
||
|
|
FREE_INT_SP();
|
||
|
|
}
|
||
|
|
#endif /* BSP_USING_TIM6 */
|
||
|
|
|
||
|
|
#ifdef BSP_USING_TIM7
|
||
|
|
void TIM7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||
|
|
void TIM7_IRQHandler(void)
|
||
|
|
{
|
||
|
|
GET_INT_SP();
|
||
|
|
rt_interrupt_enter();
|
||
|
|
ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM7_INDEX].device));
|
||
|
|
rt_interrupt_leave();
|
||
|
|
FREE_INT_SP();
|
||
|
|
}
|
||
|
|
#endif /* BSP_USING_TIM7 */
|
||
|
|
|
||
|
|
#ifdef BSP_USING_TIM8
|
||
|
|
void TIM8_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||
|
|
void TIM8_UP_IRQHandler(void)
|
||
|
|
{
|
||
|
|
GET_INT_SP();
|
||
|
|
rt_interrupt_enter();
|
||
|
|
ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM8_INDEX].device));
|
||
|
|
rt_interrupt_leave();
|
||
|
|
FREE_INT_SP();
|
||
|
|
}
|
||
|
|
#endif /* BSP_USING_TIM8 */
|
||
|
|
|
||
|
|
#ifdef BSP_USING_TIM9
|
||
|
|
void TIM9_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||
|
|
void TIM9_UP_IRQHandler(void)
|
||
|
|
{
|
||
|
|
GET_INT_SP();
|
||
|
|
rt_interrupt_enter();
|
||
|
|
ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM9_INDEX].device));
|
||
|
|
rt_interrupt_leave();
|
||
|
|
FREE_INT_SP();
|
||
|
|
}
|
||
|
|
#endif /* BSP_USING_TIM9 */
|
||
|
|
|
||
|
|
#ifdef BSP_USING_TIM10
|
||
|
|
void TIM10_UP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||
|
|
void TIM10_UP_IRQHandler(void)
|
||
|
|
{
|
||
|
|
GET_INT_SP();
|
||
|
|
rt_interrupt_enter();
|
||
|
|
ch32_hwtimer_isr(&(ch32_hwtimer_obj[TIM10_INDEX].device));
|
||
|
|
rt_interrupt_leave();
|
||
|
|
FREE_INT_SP();
|
||
|
|
}
|
||
|
|
#endif /* BSP_USING_TIM10 */
|
||
|
|
|
||
|
|
static int rt_hw_timer_init(void)
|
||
|
|
{
|
||
|
|
int i = 0;
|
||
|
|
int result = RT_EOK;
|
||
|
|
|
||
|
|
for (i = 0; i < sizeof(ch32_hwtimer_obj) / sizeof(ch32_hwtimer_obj[0]); i++)
|
||
|
|
{
|
||
|
|
ch32_hwtimer_obj[i].device.info = &ch32_hwtimer_info;
|
||
|
|
ch32_hwtimer_obj[i].device.ops = &ch32_hwtimer_ops;
|
||
|
|
result = rt_device_hwtimer_register(&ch32_hwtimer_obj[i].device,
|
||
|
|
ch32_hwtimer_obj[i].name, (void *)&ch32_hwtimer_obj[i].handle);
|
||
|
|
RT_ASSERT(result == RT_EOK);
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(rt_hw_timer_init);
|
||
|
|
|
||
|
|
#endif /* RT_USING_HWTIMER */
|
||
|
|
#endif /* BSP_USING_HWTIMER */
|