111 lines
3.4 KiB
C
111 lines
3.4 KiB
C
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/*
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* Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-11-16 Dystopia the first version
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*/
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#ifndef __COMMON_H__
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#define __COMMON_H__
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#include <c6x.h>
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#include <cslr_cgem.h>
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#include <cslr_device.h>
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#include <cslr_bootcfg.h>
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#include <cslr_tmr.h>
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#include <csl_tmr.h>
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/* DSP core clock speed in Hz */
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#define DSP_CORE_SPEED_HZ 1000000000
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extern CSL_CgemRegs * gp_cgem_regs;
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extern CSL_BootcfgRegs * gp_bootcfg_regs;
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/*----------------------Timer plus registers definition----------------*/
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typedef struct {
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volatile unsigned int PID12;
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volatile unsigned int EMUMGT_CLKSPD;
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volatile unsigned int GPINT_EN;
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volatile unsigned int GPDIR_DAT;
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volatile unsigned int CNTLO;
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volatile unsigned int CNTHI;
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volatile unsigned int PRDLO;
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volatile unsigned int PRDHI;
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volatile unsigned int TCR;
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volatile unsigned int TGCR;
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volatile unsigned int WDTCR;
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volatile unsigned int TLGC;
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volatile unsigned int TLMR;
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volatile unsigned int RELLO;
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volatile unsigned int RELHI;
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volatile unsigned int CAPLO;
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volatile unsigned int CAPHI;
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volatile unsigned int INTCTL_STAT;
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volatile unsigned char RSVD0[24];
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volatile unsigned int TIMERLO_COMPARE_REG[8];
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volatile unsigned char RSVD1[32];
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} CSL_TmrPlusRegs;
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#define TMR_TCR_READRSTMODE_HI_SHIFT (26)
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#define TMR_TCR_CAPEVTMODE_LO_SHIFT (12)
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#define TMR_TCR_CAPMODE_LO_SHIFT (11)
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#define TMR_TCR_READRSTMODE_LO_SHIFT (10)
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#define TMR_TCR_READRSTMODE_HI_MASK (1<<26)
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#define TMR_TCR_CAPEVTMODE_LO_MASK (3<<12)
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#define TMR_TCR_CAPMODE_LO_MASK (1<<11)
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#define TMR_TCR_READRSTMODE_LO_MASK (1<<10)
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#define TMR_TGCR_PLUSEN_SHIFT 4
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#define TMR_TGCR_PLUSEN_MASK (1<<4)
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#define TMR_INTCTLSTAT_EN_ALL_CLR_ALL 0x000F000F
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#define CSL_TMR_WDTCR_WDKEY_CMD1 (0x0000A5C6u)
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#define CSL_TMR_WDTCR_WDKEY_CMD2 (0x0000DA7Eu)
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#define CSL_TMR_ENAMODE_CONT_RELOAD 3
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extern CSL_TmrPlusRegs * gp_timer0_regs;
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extern CSL_TmrPlusRegs * gp_timer1_regs;
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extern CSL_TmrPlusRegs * gp_timer2_regs;
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extern CSL_TmrPlusRegs * gp_timer3_regs;
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extern CSL_TmrPlusRegs * gp_timer4_regs;
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extern CSL_TmrPlusRegs * gp_timer5_regs;
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extern CSL_TmrPlusRegs * gp_timer6_regs;
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extern CSL_TmrPlusRegs * gp_timer7_regs;
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extern CSL_TmrPlusRegs * gp_timer8_regs;
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extern CSL_TmrPlusRegs * gp_timer_regs[];
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typedef enum
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{
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TIMER_ONE_SHOT_PULSE = 0, /*generate one shot pulse with timer*/
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TIMER_PERIODIC_PULSE, /*generate periodic pulse with timer*/
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TIMER_PERIODIC_CLOCK, /*generate periodic clock with timer*/
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/*generate periodic square wave with period reload feature, the difference
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between wave and clock is the duty cycle of clock is always 50%*/
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TIMER_PERIODIC_WAVE,
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TIMER_WATCH_DOG /*configure timer as watch dog*/
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}TTimerMode;
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typedef struct {
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int timer_num; /*select one timer*/
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TTimerMode timerMode; /*select function of the timer*/
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unsigned long long period; /*in the unit of DSP core clock/6*/
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unsigned long long reload_period; /*the reload value of period*/
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int pulseWidth; /*pulse width between 0~3*/
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}Timer64_Config;
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/* Reset a 64-bit timer */
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extern void reset_timer(int timer_num);
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/* Initailize a 64-bit timer */
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extern void timer64_init(Timer64_Config * tmrCfg);
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extern void keystone_cpu_init(void);
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#endif /* __COMMON_H__ */
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