452 lines
13 KiB
C
452 lines
13 KiB
C
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/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-3-15 Wayne First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_QSPI)
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#define LOG_TAG "drv.qspi"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME LOG_TAG
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#define DBG_LEVEL DBG_INFO
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#define DBG_COLOR
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#include <rtdbg.h>
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#include <rthw.h>
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#include <rtdef.h>
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#include <drv_spi.h>
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/* Private define ---------------------------------------------------------------*/
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enum
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{
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QSPI_START = -1,
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#if defined(BSP_USING_QSPI0)
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QSPI0_IDX,
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#endif
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#if defined(BSP_USING_QSPI1)
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QSPI1_IDX,
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#endif
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QSPI_CNT
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};
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/* Private typedef --------------------------------------------------------------*/
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/* Private functions ------------------------------------------------------------*/
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static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
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static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message);
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static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name);
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/* Public functions -------------------------------------------------------------*/
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/* Private variables ------------------------------------------------------------*/
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static struct rt_spi_ops nu_qspi_poll_ops =
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{
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.configure = nu_qspi_bus_configure,
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.xfer = nu_qspi_bus_xfer,
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};
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static struct nu_spi nu_qspi_arr [] =
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{
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#if defined(BSP_USING_QSPI0)
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{
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.name = "qspi0",
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.spi_base = (SPI_T *)QSPI0,
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.rstidx = QSPI0_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_QSPI0_PDMA)
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.pdma_perp_tx = PDMA_QSPI0_TX,
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.pdma_perp_rx = PDMA_QSPI0_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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#if defined(BSP_USING_QSPI1)
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{
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.name = "qspi1",
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.spi_base = (SPI_T *)QSPI1,
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.rstidx = QSPI1_RST,
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#if defined(BSP_USING_SPI_PDMA)
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#if defined(BSP_USING_QSPI1_PDMA)
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.pdma_perp_tx = PDMA_QSPI1_TX,
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.pdma_perp_rx = PDMA_QSPI1_RX,
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#else
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.pdma_perp_tx = NU_PDMA_UNUSED,
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.pdma_perp_rx = NU_PDMA_UNUSED,
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#endif
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#endif
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},
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#endif
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}; /* qspi nu_qspi */
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static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration)
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{
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struct nu_spi *spi_bus;
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rt_uint32_t u32SPIMode;
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rt_uint32_t u32BusClock;
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rt_err_t ret = RT_EOK;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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spi_bus = (struct nu_spi *) device->bus;
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/* Check mode */
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switch (configuration->mode & RT_SPI_MODE_3)
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{
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case RT_SPI_MODE_0:
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u32SPIMode = SPI_MODE_0;
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break;
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case RT_SPI_MODE_1:
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u32SPIMode = SPI_MODE_1;
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break;
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case RT_SPI_MODE_2:
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u32SPIMode = SPI_MODE_2;
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break;
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case RT_SPI_MODE_3:
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u32SPIMode = SPI_MODE_3;
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break;
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default:
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ret = RT_EIO;
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goto exit_nu_qspi_bus_configure;
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}
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/* Check data width */
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if (!(configuration->data_width == 8 ||
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configuration->data_width == 16 ||
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configuration->data_width == 24 ||
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configuration->data_width == 32))
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{
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ret = RT_EINVAL;
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goto exit_nu_qspi_bus_configure;
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}
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/* Try to set clock and get actual spi bus clock */
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u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz);
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if (configuration->max_hz > u32BusClock)
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{
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LOG_W("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz);
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configuration->max_hz = u32BusClock;
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}
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/* Need to initialize new configuration? */
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if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(struct rt_spi_configuration)) != 0)
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{
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rt_memcpy(&spi_bus->configuration, configuration, sizeof(struct rt_spi_configuration));
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QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock);
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if (configuration->mode & RT_SPI_CS_HIGH)
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{
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/* Set CS pin to LOW */
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SPI_SET_SS_LOW(spi_bus->spi_base);
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}
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else
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{
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/* Set CS pin to HIGH */
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SPI_SET_SS_HIGH(spi_bus->spi_base);
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}
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if (configuration->mode & RT_SPI_MSB)
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{
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/* Set sequence to MSB first */
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SPI_SET_MSB_FIRST(spi_bus->spi_base);
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}
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else
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{
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/* Set sequence to LSB first */
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SPI_SET_LSB_FIRST(spi_bus->spi_base);
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}
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}
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/* Clear SPI RX FIFO */
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nu_spi_drain_rxfifo(spi_bus->spi_base);
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exit_nu_qspi_bus_configure:
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return -(ret);
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}
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static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines)
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{
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QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base;
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#if defined(RT_SFUD_USING_QSPI)
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if (qspi_lines > 1)
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{
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if (tx)
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{
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switch (qspi_lines)
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{
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case 2:
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QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi_base);
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break;
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case 4:
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QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi_base);
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break;
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default:
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LOG_E("Data line is not supported.\n");
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break;
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}
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}
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else
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{
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switch (qspi_lines)
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{
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case 2:
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QSPI_ENABLE_DUAL_INPUT_MODE(qspi_base);
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break;
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case 4:
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QSPI_ENABLE_QUAD_INPUT_MODE(qspi_base);
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break;
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default:
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LOG_E("Data line is not supported.\n");
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break;
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}
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}
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}
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else
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#endif
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{
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QSPI_DISABLE_DUAL_MODE(qspi_base);
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QSPI_DISABLE_QUAD_MODE(qspi_base);
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}
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return qspi_lines;
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}
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static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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struct nu_spi *qspi_bus;
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struct rt_qspi_configuration *qspi_configuration;
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struct rt_qspi_message *qspi_message;
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rt_uint8_t u8last = 1;
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rt_uint8_t bytes_per_word;
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QSPI_T *qspi_base;
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rt_uint32_t u32len = 0;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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qspi_bus = (struct nu_spi *) device->bus;
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qspi_base = (QSPI_T *)qspi_bus->spi_base;
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qspi_configuration = &qspi_bus->configuration;
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bytes_per_word = qspi_configuration->parent.data_width / 8;
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if (message->cs_take && !(qspi_configuration->parent.mode & RT_SPI_NO_CS))
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{
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if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH)
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{
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QSPI_SET_SS_HIGH(qspi_base);
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}
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else
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{
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QSPI_SET_SS_LOW(qspi_base);
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}
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}
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qspi_message = (struct rt_qspi_message *)message;
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/* Command + Address + Dummy + Data */
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/* Command stage */
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if (qspi_message->instruction.content != 0)
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{
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u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines);
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nu_spi_transfer((struct nu_spi *)qspi_bus,
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(rt_uint8_t *) &qspi_message->instruction.content,
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RT_NULL,
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1,
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1);
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}
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/* Address stage */
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if (qspi_message->address.size > 0)
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{
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rt_uint32_t u32ReversedAddr = 0;
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rt_uint32_t u32AddrNumOfByte = qspi_message->address.size / 8;
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switch (u32AddrNumOfByte)
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{
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case 1:
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u32ReversedAddr = (qspi_message->address.content & 0xff);
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break;
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case 2:
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nu_set16_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
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break;
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case 3:
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nu_set24_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
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break;
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case 4:
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nu_set32_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
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break;
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default:
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RT_ASSERT(0);
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break;
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}
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u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines);
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nu_spi_transfer((struct nu_spi *)qspi_bus,
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(rt_uint8_t *) &u32ReversedAddr,
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RT_NULL,
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u32AddrNumOfByte,
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1);
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}
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/* alternate_bytes stage */
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if ((qspi_message->alternate_bytes.size > 0) && (qspi_message->alternate_bytes.size <= 4))
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{
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rt_uint32_t u32AlternateByte = 0;
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rt_uint32_t u32NumOfByte = qspi_message->alternate_bytes.size / 8;
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switch (u32NumOfByte)
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{
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case 1:
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u32AlternateByte = (qspi_message->alternate_bytes.content & 0xff);
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break;
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case 2:
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nu_set16_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content);
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break;
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case 3:
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nu_set24_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content);
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break;
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case 4:
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nu_set32_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content);
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break;
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default:
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RT_ASSERT(0);
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break;
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}
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u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *)&u32AlternateByte, RT_NULL, qspi_message->alternate_bytes.qspi_lines);
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nu_spi_transfer((struct nu_spi *)qspi_bus,
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(rt_uint8_t *) &u32AlternateByte,
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RT_NULL,
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u32NumOfByte,
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1);
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}
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/* Dummy_cycles stage */
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if (qspi_message->dummy_cycles > 0)
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{
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qspi_bus->dummy = 0x00;
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u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_bus->dummy, RT_NULL, u8last);
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nu_spi_transfer((struct nu_spi *)qspi_bus,
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(rt_uint8_t *) &qspi_bus->dummy,
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RT_NULL,
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qspi_message->dummy_cycles / (8 / u8last),
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1);
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}
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if (message->length > 0)
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{
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/* Data stage */
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nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
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nu_spi_transfer((struct nu_spi *)qspi_bus,
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(rt_uint8_t *) message->send_buf,
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(rt_uint8_t *) message->recv_buf,
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message->length,
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bytes_per_word);
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u32len = message->length;
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}
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else
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{
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u32len = 1;
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}
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if (message->cs_release && !(qspi_configuration->parent.mode & RT_SPI_NO_CS))
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{
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if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH)
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{
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||
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|
QSPI_SET_SS_LOW(qspi_base);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
QSPI_SET_SS_HIGH(qspi_base);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return u32len;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name)
|
||
|
|
{
|
||
|
|
return rt_qspi_bus_register(&qspi_bus->dev, name, &nu_qspi_poll_ops);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Hardware SPI Initial
|
||
|
|
*/
|
||
|
|
static int rt_hw_qspi_init(void)
|
||
|
|
{
|
||
|
|
rt_uint8_t i;
|
||
|
|
|
||
|
|
for (i = (QSPI_START + 1); i < QSPI_CNT; i++)
|
||
|
|
{
|
||
|
|
SYS_ResetModule(nu_qspi_arr[i].rstidx);
|
||
|
|
|
||
|
|
nu_qspi_register_bus(&nu_qspi_arr[i], nu_qspi_arr[i].name);
|
||
|
|
#if defined(BSP_USING_SPI_PDMA)
|
||
|
|
nu_qspi_arr[i].pdma_chanid_tx = -1;
|
||
|
|
nu_qspi_arr[i].pdma_chanid_rx = -1;
|
||
|
|
#endif
|
||
|
|
#if defined(BSP_USING_QSPI_PDMA)
|
||
|
|
if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
|
||
|
|
{
|
||
|
|
if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_E("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_qspi_init);
|
||
|
|
|
||
|
|
rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
|
||
|
|
{
|
||
|
|
struct rt_qspi_device *qspi_device = RT_NULL;
|
||
|
|
rt_err_t result = RT_EOK;
|
||
|
|
|
||
|
|
RT_ASSERT(bus_name != RT_NULL);
|
||
|
|
RT_ASSERT(device_name != RT_NULL);
|
||
|
|
RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
|
||
|
|
|
||
|
|
qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
|
||
|
|
if (qspi_device == RT_NULL)
|
||
|
|
{
|
||
|
|
LOG_E("no memory, qspi bus attach device failed!\n");
|
||
|
|
result = -RT_ENOMEM;
|
||
|
|
goto __exit;
|
||
|
|
}
|
||
|
|
|
||
|
|
qspi_device->enter_qspi_mode = enter_qspi_mode;
|
||
|
|
qspi_device->exit_qspi_mode = exit_qspi_mode;
|
||
|
|
qspi_device->config.qspi_dl_width = data_line_width;
|
||
|
|
|
||
|
|
result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, RT_NULL);
|
||
|
|
|
||
|
|
__exit:
|
||
|
|
if (result != RT_EOK)
|
||
|
|
{
|
||
|
|
if (qspi_device)
|
||
|
|
{
|
||
|
|
rt_free(qspi_device);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif //#if defined(BSP_USING_QSPI)
|