355 lines
11 KiB
C
355 lines
11 KiB
C
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/*
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* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Change Logs:
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* Date Author Notes
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* 2019-3-19 wangyq the first version
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* 2019-11-01 wangyq update libraries
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* 2021-04-20 liuhy the second version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <drv_hwtimer.h>
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#include <board.h>
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#ifdef RT_USING_HWTIMER
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struct es32f3_hwtimer_dev
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{
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rt_hwtimer_t parent;
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ald_timer_handle_t *hwtimer_periph;
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IRQn_Type IRQn;
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};
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#ifdef BSP_USING_AD16C4T0_HWTIMER
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static struct es32f3_hwtimer_dev ad16c4t0_hwtimer;
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static struct rt_hwtimer_info ad16c4t0_info =
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{
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ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
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(ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */
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0xFFFF, /* counter maximum value */
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ES_AD16C4T0_HWTIMER_MODE
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};
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void __attribute__((interrupt)) AD16C4T_Handler(void)
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{
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rt_interrupt_enter();
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ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, ALD_TIMER_FLAG_UPDATE);
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rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent);
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_GP16C4T0_HWTIMER
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static struct es32f3_hwtimer_dev gp16c4t0_hwtimer;
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static struct rt_hwtimer_info gp16c4t0_info =
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{
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ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
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(ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */
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0xFFFF, /* counter maximum value */
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ES_GP16C4T0_HWTIMER_MODE
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};
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void __attribute__((interrupt)) GPTIMB0_Handler(void)
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{
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rt_interrupt_enter();
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ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
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rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent);
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_GP16C4T1_HWTIMER
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static struct es32f3_hwtimer_dev gp16c4t1_hwtimer;
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static struct rt_hwtimer_info gp16c4t1_info =
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{
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ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
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(ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */
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0xFFFF, /* counter maximum value */
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ES_GP16C4T1_HWTIMER_MODE
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};
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void __attribute__((interrupt)) GPTIMB1_Handler(void)
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{
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rt_interrupt_enter();
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ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
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rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent);
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_GP16C4T1_HWTIMER
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static struct es32f3_hwtimer_dev gp16c4t1_hwtimer;
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static struct rt_hwtimer_info gp16c4t1_info =
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{
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ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
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(ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */
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0xFFFF, /* counter maximum value */
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ES_GP16C4T1_HWTIMER_MODE
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};
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void __attribute__((interrupt)) GPTIMB2_Handler(void)
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{
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rt_interrupt_enter();
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ald_timer_clear_flag_status(gp16c4t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
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rt_device_hwtimer_isr(&gp16c4t1_hwtimer.parent);
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_BS16T0_HWTIMER
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static struct es32f3_hwtimer_dev bs16t0_hwtimer;
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static struct rt_hwtimer_info bs16t0_info =
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{
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ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV, /* maximum count frequency */
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(ES_SYS_HCLK_CLK >> ES_CMU_PCLK_DIV)/(1U<<16), /* minimum count frequency */
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0xFFFF, /* counter maximum value */
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ES_BS16T0_HWTIMER_MODE
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};
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void __attribute__((interrupt)) BSTIM0_Handler(void)
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{
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rt_interrupt_enter();
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ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
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rt_device_hwtimer_isr(&bs16t0_hwtimer.parent);
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rt_interrupt_leave();
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}
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#endif
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static void es32f3_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
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{
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struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
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struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info;
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RT_ASSERT(hwtimer != RT_NULL);
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if (1 == state)
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{
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ald_timer_base_init(hwtimer->hwtimer_periph);
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ald_timer_interrupt_config(hwtimer->hwtimer_periph, ALD_TIMER_IT_UPDATE, ENABLE);
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csi_vic_enable_sirq(hwtimer->IRQn);
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}
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hwtimer->parent.freq = ald_cmu_get_pclk_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1);
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hwtimer_info->maxfreq = hwtimer->parent.freq;
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hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF;
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}
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static rt_err_t es32f3_hwtimer_start(rt_hwtimer_t *timer,
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rt_uint32_t cnt,
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rt_hwtimer_mode_t mode)
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{
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struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
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RT_ASSERT(hwtimer != RT_NULL);
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WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt);
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ald_timer_base_start(hwtimer->hwtimer_periph);
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return RT_EOK;
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}
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static void es32f3_hwtimer_stop(rt_hwtimer_t *timer)
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{
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struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
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RT_ASSERT(hwtimer != RT_NULL);
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ald_timer_base_stop(hwtimer->hwtimer_periph);
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}
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static rt_uint32_t es32f3_hwtimer_count_get(rt_hwtimer_t *timer)
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{
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struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
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uint32_t hwtimer_count = 0;
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RT_ASSERT(hwtimer != RT_NULL);
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hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT);
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return hwtimer_count;
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}
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static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer,
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rt_uint32_t cmd,
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void *args)
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{
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rt_err_t ret = RT_EOK;
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rt_uint32_t freq = 0;
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struct es32f3_hwtimer_dev *hwtimer = (struct es32f3_hwtimer_dev *)timer->parent.user_data;
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RT_ASSERT(hwtimer != RT_NULL);
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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freq = *(rt_uint32_t *)args;
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ret = -RT_ERROR;
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if(freq)
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{
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double temp,target;
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temp = (double)ald_cmu_get_pclk_clock();
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target = temp/freq;
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if(target < 0x10001) /*最大分频 = max(PRES)+1*/
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{
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temp = target - (int)(target);
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if((temp > 0.998)&&(target < 0x10000))
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{
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hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target;
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ret = RT_EOK;
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}
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if((temp < 0.002)&&(target >= 0x1))
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{
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hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1;
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ret = RT_EOK;
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}
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}
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if(ret == RT_EOK) /*更新信息*/
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hwtimer->parent.freq = ald_cmu_get_pclk_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1);
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}
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break;
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case HWTIMER_CTRL_STOP:
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ald_timer_base_stop(hwtimer->hwtimer_periph);
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break;
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default:
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ret = RT_EINVAL;
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break;
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}
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return ret;
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}
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static struct rt_hwtimer_ops es32f3_hwtimer_ops =
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{
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es32f3_hwtimer_init,
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es32f3_hwtimer_start,
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es32f3_hwtimer_stop,
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es32f3_hwtimer_count_get,
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es32f3_hwtimer_control
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};
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int rt_hw_hwtimer_init(void)
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{
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rt_err_t ret = RT_EOK;
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#ifdef BSP_USING_AD16C4T0_HWTIMER
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static ald_timer_handle_t ad16c4t0_hwtimer_periph;
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ad16c4t0_hwtimer_periph.perh = AD16C4T;
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ad16c4t0_hwtimer.IRQn = AD16C4T_IRQn;
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ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1;
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ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? ALD_TIMER_CNT_MODE_UP : ALD_TIMER_CNT_MODE_DOWN;
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ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph;
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ad16c4t0_hwtimer.parent.info = &ad16c4t0_info;
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ad16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
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ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer);
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#endif
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#ifdef BSP_USING_GP16C4T0_HWTIMER
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static timer_handle_t gp16c4t0_hwtimer_periph;
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gp16c4t0_hwtimer_periph.perh = GP16C4T0;
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gp16c4t0_hwtimer.IRQn = GP16C4T0_IRQn;
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gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1;
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gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
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gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph;
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gp16c4t0_hwtimer.parent.info = &gp16c4t0_info;
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gp16c4t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
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ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer);
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#endif
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#ifdef BSP_USING_GP16C4T1_HWTIMER
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static timer_handle_t gp16c4t1_hwtimer_periph;
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gp16c4t1_hwtimer_periph.perh = GP16C4T1;
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gp16c4t1_hwtimer.IRQn = GP16C4T1_IRQn;
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gp16c4t1_hwtimer_periph.init.prescaler = ES_GP16C4T1_HWTIMER_PRES - 1;
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gp16c4t1_hwtimer_periph.init.mode = ( ES_GP16C4T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
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gp16c4t1_hwtimer.hwtimer_periph = &gp16c4t1_hwtimer_periph;
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gp16c4t1_hwtimer.parent.info = &gp16c4t1_info;
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gp16c4t1_hwtimer.parent.ops = &es32f3_hwtimer_ops;
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ret = rt_device_hwtimer_register(&gp16c4t1_hwtimer.parent, ES_DEVICE_NAME_GP16C4T1_HWTIMER, &gp16c4t1_hwtimer);
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#endif
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#ifdef BSP_USING_GP16C4T2_HWTIMER
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static timer_handle_t gp16c4t2_hwtimer_periph;
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gp16c4t2_hwtimer_periph.perh = GP16C4T2;
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gp16c4t2_hwtimer.IRQn = GP16C4T2_IRQn;
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gp16c4t2_hwtimer_periph.init.prescaler = ES_GP16C4T2_HWTIMER_PRES - 1;
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gp16c4t2_hwtimer_periph.init.mode = ( ES_GP16C4T2_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
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gp16c4t2_hwtimer.hwtimer_periph = &gp16c4t2_hwtimer_periph;
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gp16c4t2_hwtimer.parent.info = &gp16c4t2_info;
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gp16c4t2_hwtimer.parent.ops = &es32f3_hwtimer_ops;
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ret = rt_device_hwtimer_register(&gp16c4t2_hwtimer.parent, ES_DEVICE_NAME_GP16C4T2_HWTIMER, &gp16c4t2_hwtimer);
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#endif
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||
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#ifdef BSP_USING_BS16T0_HWTIMER
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static timer_handle_t bs16t0_hwtimer_periph;
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||
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bs16t0_hwtimer_periph.perh = BS16T0;
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bs16t0_hwtimer.IRQn = BS16T0_IRQn;
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||
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||
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bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1;
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bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
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||
|
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bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph;
|
||
|
|
|
||
|
|
bs16t0_hwtimer.parent.info = &bs16t0_info;
|
||
|
|
bs16t0_hwtimer.parent.ops = &es32f3_hwtimer_ops;
|
||
|
|
ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
|
||
|
|
|
||
|
|
#endif
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