2017-07-30 15:34:32 +08:00
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;/*
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; * File : start_gcc.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * This program is free software; you can redistribute it and/or modify
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; * it under the terms of the GNU General Public License as published by
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; * the Free Software Foundation; either version 2 of the License, or
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; * (at your option) any later version.
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; *
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; * This program is distributed in the hope that it will be useful,
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; * but WITHOUT ANY WARRANTY; without even the implied warranty of
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; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; * GNU General Public License for more details.
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; *
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; * You should have received a copy of the GNU General Public License along
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; * with this program; if not, write to the Free Software Foundation, Inc.,
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; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2017-07-16 zhangjun for hifive1
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; */
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2017-07-17 15:44:00 +08:00
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#include <sifive/smp.h>
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#define CLINT_CTRL_ADDR 0x02000000
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2017-07-30 15:34:32 +08:00
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.section .init
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.globl _start
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.type _start,@function
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2017-07-17 15:44:00 +08:00
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_start:
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.cfi_startproc
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.cfi_undefined ra
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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la sp, _sp
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2017-07-30 19:46:28 +08:00
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/*
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*disable all interrupt at startup
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*/
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csrrc a5, mstatus, 0xb
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2017-07-17 15:44:00 +08:00
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#if defined(ENABLE_SMP)
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smp_pause(t0, t1)
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#endif
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/* Load data section */
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la a0, _data_lma
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la a1, _data
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la a2, _edata
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bgeu a1, a2, 2f
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1:
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lw t0, (a0)
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sw t0, (a1)
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addi a0, a0, 4
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addi a1, a1, 4
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bltu a1, a2, 1b
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2:
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/* Clear bss section */
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la a0, __bss_start
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la a1, _end
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bgeu a0, a1, 2f
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1:
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sw zero, (a0)
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addi a0, a0, 4
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bltu a0, a1, 1b
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2:
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/* Call global constructors */
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la a0, __libc_fini_array
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call atexit
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call __libc_init_array
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2017-07-30 19:46:28 +08:00
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/*call _init directly in rt-thread*/
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2017-07-26 16:07:01 +08:00
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call _init
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2017-07-17 15:44:00 +08:00
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#ifndef __riscv_float_abi_soft
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/* Enable FPU */
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li t0, MSTATUS_FS
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csrs mstatus, t0
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csrr t1, mstatus
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and t1, t1, t0
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beqz t1, 1f
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fssr x0
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1:
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#endif
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#if defined(ENABLE_SMP)
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smp_resume(t0, t1)
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csrr a0, mhartid
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bnez a0, 2f
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#endif
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auipc ra, 0
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addi sp, sp, -16
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#if __riscv_xlen == 32
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sw ra, 8(sp)
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#else
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sd ra, 8(sp)
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#endif
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/* argc = argv = 0 */
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li a0, 0
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li a1, 0
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call main
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tail exit
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1:
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j 1b
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#if defined(ENABLE_SMP)
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2:
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la t0, trap_entry
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csrw mtvec, t0
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csrr a0, mhartid
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la t1, _sp
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slli t0, a0, 10
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sub sp, t1, t0
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auipc ra, 0
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addi sp, sp, -16
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#if __riscv_xlen == 32
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sw ra, 8(sp)
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#else
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sd ra, 8(sp)
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#endif
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call secondary_main
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tail exit
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1:
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j 1b
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#endif
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.cfi_endproc
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2017-07-26 16:07:01 +08:00
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#include "encoding.h"
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#include "sifive/bits.h"
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.section .text.entry
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.align 2
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.global trap_entry
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trap_entry:
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2017-07-30 15:34:32 +08:00
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addi sp, sp, -32*REGBYTES
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2017-07-26 16:07:01 +08:00
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STORE x30, 1*REGBYTES(sp)
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STORE x31, 2*REGBYTES(sp)
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2017-07-29 15:37:20 +08:00
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STORE x3, 3*REGBYTES(sp)
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STORE x4, 4*REGBYTES(sp)
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STORE x5, 5*REGBYTES(sp)
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STORE x6, 6*REGBYTES(sp)
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STORE x7, 7*REGBYTES(sp)
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STORE x8, 8*REGBYTES(sp)
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STORE x9, 9*REGBYTES(sp)
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2017-07-26 16:07:01 +08:00
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STORE x10, 10*REGBYTES(sp)
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STORE x11, 11*REGBYTES(sp)
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STORE x12, 12*REGBYTES(sp)
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STORE x13, 13*REGBYTES(sp)
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STORE x14, 14*REGBYTES(sp)
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STORE x15, 15*REGBYTES(sp)
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STORE x16, 16*REGBYTES(sp)
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STORE x17, 17*REGBYTES(sp)
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STORE x18, 18*REGBYTES(sp)
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STORE x19, 19*REGBYTES(sp)
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STORE x20, 20*REGBYTES(sp)
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STORE x21, 21*REGBYTES(sp)
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STORE x22, 22*REGBYTES(sp)
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STORE x23, 23*REGBYTES(sp)
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STORE x24, 24*REGBYTES(sp)
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STORE x25, 25*REGBYTES(sp)
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STORE x26, 26*REGBYTES(sp)
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STORE x27, 27*REGBYTES(sp)
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STORE x28, 28*REGBYTES(sp)
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STORE x10, 29*REGBYTES(sp)
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2017-07-29 15:37:20 +08:00
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STORE x1, 30*REGBYTES(sp)
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2017-07-30 15:34:32 +08:00
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csrr x10, mepc
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STORE x10, 31*REGBYTES(sp)
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2017-07-31 10:59:59 +08:00
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csrr x10, mie
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STORE x10, 0*REGBYTES(sp)
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2017-07-26 16:07:01 +08:00
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2017-07-31 10:59:59 +08:00
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/*
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*Remain in M-mode after mret
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*enable interrupt in M-mode
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*/
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li t0, MSTATUS_MPP
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csrrs t0, mstatus, t0
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2017-07-26 16:07:01 +08:00
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call rt_interrupt_enter
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2017-07-30 19:46:28 +08:00
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csrr a0, mcause
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lui a5, 0x80000
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not a5, a5
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and a5, a5, a0
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li a4, 11
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mv s1, a1
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/*Machine external interrupt*/
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bne a5, a4, 1f
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2017-07-26 16:07:01 +08:00
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call rt_hw_trap_irq
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2017-07-30 19:46:28 +08:00
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1:
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2017-07-31 10:59:59 +08:00
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/*Machine timer interrupt*/
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2017-07-30 19:46:28 +08:00
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li a4, 7
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bne a5, a4, 2f
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call rt_systick_handler
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2:
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2017-07-26 16:07:01 +08:00
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call rt_interrupt_leave
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2017-07-30 19:46:28 +08:00
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la a0, rt_thread_switch_interrupt_flag
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lw a1, (a0)
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2017-07-30 15:34:32 +08:00
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bnez a1, rt_hw_context_switch_interrupt_do
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2017-07-26 16:07:01 +08:00
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LOAD x30, 1*REGBYTES(sp)
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LOAD x31, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x29, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x10, 31*REGBYTES(sp)
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2017-07-30 15:34:32 +08:00
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csrw mepc,x10
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2017-07-31 10:59:59 +08:00
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LOAD x10, 0*REGBYTES(sp)
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csrw mie, x10
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2017-07-26 16:07:01 +08:00
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LOAD x10, 29*REGBYTES(sp)
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LOAD x1, 30*REGBYTES(sp)
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2017-07-30 15:34:32 +08:00
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addi sp, sp, 32*REGBYTES
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2017-07-26 16:07:01 +08:00
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mret
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rt_hw_context_switch_interrupt_do:
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2017-07-30 19:46:28 +08:00
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/*clear rt_thread_switch_interrupt_flag*/
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2017-07-30 15:34:32 +08:00
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la a0, rt_thread_switch_interrupt_flag
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li a5, 0
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sw a5, (a0)
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2017-07-30 19:46:28 +08:00
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LOAD a0, rt_interrupt_from_thread
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STORE sp, (a0)
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2017-07-30 15:34:32 +08:00
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LOAD a0, rt_interrupt_to_thread
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LOAD sp, (a0)
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2017-07-26 16:07:01 +08:00
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LOAD x30, 1*REGBYTES(sp)
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LOAD x31, 2*REGBYTES(sp)
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LOAD x3, 3*REGBYTES(sp)
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LOAD x4, 4*REGBYTES(sp)
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LOAD x5, 5*REGBYTES(sp)
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LOAD x6, 6*REGBYTES(sp)
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LOAD x7, 7*REGBYTES(sp)
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LOAD x8, 8*REGBYTES(sp)
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LOAD x9, 9*REGBYTES(sp)
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LOAD x29, 10*REGBYTES(sp)
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LOAD x11, 11*REGBYTES(sp)
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LOAD x12, 12*REGBYTES(sp)
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LOAD x13, 13*REGBYTES(sp)
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LOAD x14, 14*REGBYTES(sp)
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LOAD x15, 15*REGBYTES(sp)
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LOAD x16, 16*REGBYTES(sp)
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LOAD x17, 17*REGBYTES(sp)
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LOAD x18, 18*REGBYTES(sp)
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LOAD x19, 19*REGBYTES(sp)
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LOAD x20, 20*REGBYTES(sp)
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LOAD x21, 21*REGBYTES(sp)
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LOAD x22, 22*REGBYTES(sp)
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LOAD x23, 23*REGBYTES(sp)
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LOAD x24, 24*REGBYTES(sp)
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LOAD x25, 25*REGBYTES(sp)
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LOAD x26, 26*REGBYTES(sp)
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LOAD x27, 27*REGBYTES(sp)
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LOAD x28, 28*REGBYTES(sp)
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LOAD x10, 31*REGBYTES(sp)
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2017-07-30 15:34:32 +08:00
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csrw mepc,x10
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2017-07-31 10:59:59 +08:00
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LOAD x10, 0*REGBYTES(sp)
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csrw mie, x10
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2017-07-26 16:07:01 +08:00
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LOAD x10, 29*REGBYTES(sp)
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LOAD x1, 30*REGBYTES(sp)
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addi sp, sp, 32*REGBYTES
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mret
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