286 lines
14 KiB
C
286 lines
14 KiB
C
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/*!
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*******************************************************************************
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**
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** \file gh_vic.h
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**
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** \brief VIC.
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**
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** Copyright: 2012 - 2016 (C) GoKe Microelectronics
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**
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** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
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** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
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** OMMISSIONS.
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**
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** \note Do not modify this file as it is generated automatically.
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**
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******************************************************************************/
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#ifndef _GH_VIC_H
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#define _GH_VIC_H
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#ifdef __LINUX__
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#include "reg4linux.h"
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#else
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#define FIO_ADDRESS(block,address) (address)
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#define FIO_MOFFSET(block,moffset) (moffset)
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#endif
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#ifndef __LINUX__
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#include "gtypes.h" /* global type definitions */
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#include "gh_lib_cfg.h" /* configuration */
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#endif
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#define GH_VIC_ENABLE_DEBUG_PRINT 0
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#ifdef __LINUX__
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#define GH_VIC_DEBUG_PRINT_FUNCTION printk
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#else
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#define GH_VIC_DEBUG_PRINT_FUNCTION printf
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#endif
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#ifndef __LINUX__
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#if GH_VIC_ENABLE_DEBUG_PRINT
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#include <stdio.h>
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#endif
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#endif
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/*----------------------------------------------------------------------------*/
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/* registers */
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/*----------------------------------------------------------------------------*/
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#define REG_VIC_IRQSTS FIO_ADDRESS(VIC,0x90003030) /* read */
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#define REG_VIC_FIQSTS FIO_ADDRESS(VIC,0x90003034) /* read */
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#define REG_VIC_RAWSTS FIO_ADDRESS(VIC,0x90003018) /* read */
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#define REG_VIC_SELECT FIO_ADDRESS(VIC,0x9000300C) /* read/write */
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#define REG_VIC_ENABLE FIO_ADDRESS(VIC,0x90003010) /* read/write */
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#define REG_VIC_ENCLR FIO_ADDRESS(VIC,0x90003014) /* write */
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#define REG_VIC_SOFTINT FIO_ADDRESS(VIC,0x9000301C) /* read/write */
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#define REG_VIC_SOFTINTRCLR FIO_ADDRESS(VIC,0x90003020) /* write */
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#define REG_VIC_PROTECT FIO_ADDRESS(VIC,0x90003024) /* read/write */
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#define REG_VIC_SENSE FIO_ADDRESS(VIC,0x90003000) /* read/write */
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#define REG_VIC_BOTHEDGE FIO_ADDRESS(VIC,0x90003008) /* read/write */
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#define REG_VIC_EVENT FIO_ADDRESS(VIC,0x90003004) /* read/write */
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#define REG_VIC_EDGECLR FIO_ADDRESS(VIC,0x90003038) /* write */
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/*!
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*******************************************************************************
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**
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** \brief Interrupt vectors
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**
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** The list below describes all available interrupt sources,
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** a table containing the real interrupt service routines.
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** All other interrupts are maskable and the priority can be set
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** either to medium (1) or low (2).
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**
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******************************************************************************/
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enum
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{
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GH_INT_SSI_SLAVE_IRQ = 0, //!<
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GH_INT_ETH_IRQ = 1, //!< level, Ethernet 1
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GH_INT_IDSP_ERROR_IRQ = 2, //!< edge, iDSP error
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GH_INT_RESERVED1_03_IRQ = 3, //!<
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GH_INT_RESERVED1_04_IRQ = 4, //!<
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GH_INT_RESERVED1_05_IRQ = 5, //!<
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GH_INT_RESERVED1_06_IRQ = 6, //!<
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GH_INT_CODING_ORC_VOUT1_IRQ = 7, //!<
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GH_INT_SD_CONTROLLER_IRQ = 8, //!< level, SD controller
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GH_INT_IDC_IRQ = 9, //!< level, i2c read/write, I2C0
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GH_INT_SSI_SPI_IRQ = 10, //!< level, Synchronous Serial Interface (SSI, SPI)
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GH_INT_WDT_IRQ = 11, //!< edge, Watchdog (WDT)
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GH_INT_IRIF_IRQ = 12, //!<
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GH_INT_RESERVED1_13_IRQ = 13, //!<
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GH_INT_SD_CARD_DETECT_IRQ = 14, //!< Both edges, SD card detect (state of SMIO5 pin)
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GH_INT_UART1_IRQ = 15, //!< level, uart read/write, UART1
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GH_INT_GPIO0_IRQ = 16, //!< level, GPIO0
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GH_INT_UART2_IRQ = 17, //!< level, uart read/write, UART1
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GH_INT_TIMER1_IRQ = 18, //!< edge, timer#1
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GH_INT_TIMER2_IRQ = 19, //!< edge, timer#2
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GH_INT_TIMER3_IRQ = 20, //!< edge, timer#3
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GH_INT_DMA_IRQ = 21, //!< level, DMA
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GH_INT_RESERVED1_22_IRQ = 22, //!<
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GH_INT_RESERVED1_23_IRQ = 23, //!<
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GH_INT_CODING_ORC_VIN_IRQ = 24, //!< edge, Coding Orc VIN
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GH_INT_CORDING_ORC_VDSP_IRQ = 25, //!<
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GH_INT_USB_IRQ = 26, //!< level, USB
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GH_INT_RESERVED1_27_IRQ = 27, //!<
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GH_INT_XIU_TIMEOUT_IRQ = 28, //!<
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GH_INT_AUDIO_I2S_TX_IRQ = 29, //!< level, Audio (I2S) TX
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GH_INT_AUDIO_I2S_RX_IRQ = 30, //!< level, Audio (I2S) RX
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GH_INT_UART_IRQ = 31, //!< level, GPIO0
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GH_INT_RESERVED2_00_IRQ = ( 0 + 32), //!<
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GH_INT_RESERVED2_01_IRQ = ( 1 + 32), //!<
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GH_INT_RESERVED2_02_IRQ = ( 2 + 32), //!<
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GH_INT_RESERVED2_03_IRQ = ( 3 + 32), //!<
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GH_INT_RESERVED2_04_IRQ = ( 4 + 32), //!<
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GH_INT_RESERVED2_05_IRQ = ( 5 + 32), //!<
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GH_INT_RESERVED2_06_IRQ = ( 6 + 32), //!<
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GH_INT_RESERVED2_07_IRQ = ( 7 + 32), //!<
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GH_INT_AUDIO_PHY_RX_IRQ = ( 8 + 32), //!<
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GH_INT_AUDIO_PHY_TX_IRQ = ( 9 + 32), //!<
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GH_INT_RESERVED2_10_IRQ = ( 10 + 32), //!<
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GH_INT_RESERVED2_11_IRQ = ( 11 + 32), //!<
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GH_INT_RESERVED2_12_IRQ = ( 12 + 32), //!<
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GH_INT_RESERVED2_13_IRQ = ( 13 + 32), //!<
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GH_INT_RESERVED2_14_IRQ = ( 14 + 32), //!<
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GH_INT_RESERVED2_15_IRQ = ( 15 + 32), //!<
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GH_INT_RESERVED2_16_IRQ = ( 16 + 32), //!< edge, iDSP Vsync (VIN on master mode)
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GH_INT_RESERVED2_17_IRQ = ( 17 + 32), //!<
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GH_INT_CODING_ORC_VOUT0_IRQ = ( 18 + 32), //!<
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GH_INT_AES_OUTPUT_READY_IRQ = ( 19 + 32), //!< edge, AES output ready from Crypt block
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GH_INT_DES_OUTPUT_READY_IRQ = ( 20 + 32), //!< edge, DES output ready from Crypt block
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GH_INT_RESERVED2_21_IRQ = ( 21 + 32), //!<
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GH_INT_GDMA_COMPLETION_IRQ = ( 22 + 32), //!<
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GH_INT_MOTOR_INTERRUPT_IRQ = ( 23 + 32), //!<
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GH_INT_ADC_LEVEL_CHANGE_IRQ = ( 24 + 32), //!< level, ADC level change
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GH_INT_RESERVED2_25_IRQ = ( 25 + 32), //!<
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GH_INT_IDC2_IRQ = ( 26 + 32), //!< level, IDC2
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GH_INT_IDSP_LAST_PIXEL_IRQ = ( 27 + 32), //!< edge, iDSP last pixel
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GH_INT_IDSP_VSYNC_IRQ = ( 28 + 32), //!< edge, iDSP Vsync (VIN on master mode)
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GH_INT_IDSP_SENSOR_VSYNC_IRQ= ( 29 + 32), //!< edge, iDSP sensor Vsync (VIN on slave mode)
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GH_INT_PMU_IRQ = ( 30 + 32), //!< level, PMU
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GH_INT_SSI2_IRQ = ( 31 + 32), //!< level, SSI2
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};
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/*----------------------------------------------------------------------------*/
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/* bit group structures */
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/*----------------------------------------------------------------------------*/
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typedef union { /* VIC_Protect */
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U32 all;
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struct {
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U32 protect : 1;
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U32 : 31;
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} bitc;
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} GH_VIC_PROTECT_S;
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/*----------------------------------------------------------------------------*/
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/* mirror variables */
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/*----------------------------------------------------------------------------*/
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extern U32 m_vic_enclr[2];
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extern U32 m_vic_softintrclr[2];
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extern U32 m_vic_edgeclr[2];
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* register VIC_IRQSts (read) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Reads the register 'VIC_IRQSts'. */
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U32 GH_VIC_get_IRQSts(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_FIQSts (read) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Reads the register 'VIC_FIQSts'. */
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U32 GH_VIC_get_FIQSts(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_RawSts (read) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Reads the register 'VIC_RawSts'. */
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U32 GH_VIC_get_RawSts(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_Select (read/write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_Select'. */
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void GH_VIC_set_Select(U8 index, U32 data);
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/*! \brief Reads the register 'VIC_Select'. */
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U32 GH_VIC_get_Select(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_Enable (read/write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_Enable'. */
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void GH_VIC_set_Enable(U8 index, U32 data);
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/*! \brief Reads the register 'VIC_Enable'. */
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U32 GH_VIC_get_Enable(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_EnClr (write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_EnClr'. */
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void GH_VIC_set_EnClr(U8 index, U32 data);
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/*! \brief Reads the mirror variable of the register 'VIC_EnClr'. */
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U32 GH_VIC_getm_EnClr(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_SoftInt (read/write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_SoftInt'. */
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void GH_VIC_set_SoftInt(U8 index, U32 data);
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/*! \brief Reads the register 'VIC_SoftInt'. */
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U32 GH_VIC_get_SoftInt(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_SoftIntrClr (write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_SoftIntrClr'. */
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void GH_VIC_set_SoftIntrClr(U8 index, U32 data);
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/*! \brief Reads the mirror variable of the register 'VIC_SoftIntrClr'. */
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U32 GH_VIC_getm_SoftIntrClr(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_Protect (read/write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_Protect'. */
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void GH_VIC_set_Protect(U8 index, U32 data);
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/*! \brief Reads the register 'VIC_Protect'. */
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U32 GH_VIC_get_Protect(U8 index);
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/*! \brief Writes the bit group 'Protect' of register 'VIC_Protect'. */
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void GH_VIC_set_Protect_Protect(U8 index, U8 data);
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/*! \brief Reads the bit group 'Protect' of register 'VIC_Protect'. */
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U8 GH_VIC_get_Protect_Protect(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_Sense (read/write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_Sense'. */
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void GH_VIC_set_Sense(U8 index, U32 data);
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/*! \brief Reads the register 'VIC_Sense'. */
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U32 GH_VIC_get_Sense(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_BothEdge (read/write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_BothEdge'. */
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void GH_VIC_set_BothEdge(U8 index, U32 data);
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/*! \brief Reads the register 'VIC_BothEdge'. */
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U32 GH_VIC_get_BothEdge(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_Event (read/write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_Event'. */
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void GH_VIC_set_Event(U8 index, U32 data);
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/*! \brief Reads the register 'VIC_Event'. */
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U32 GH_VIC_get_Event(U8 index);
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/*----------------------------------------------------------------------------*/
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/* register VIC_EdgeClr (write) */
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/*----------------------------------------------------------------------------*/
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/*! \brief Writes the register 'VIC_EdgeClr'. */
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void GH_VIC_set_EdgeClr(U8 index, U32 data);
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/*! \brief Reads the mirror variable of the register 'VIC_EdgeClr'. */
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U32 GH_VIC_getm_EdgeClr(U8 index);
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/*----------------------------------------------------------------------------*/
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/* init function */
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/*----------------------------------------------------------------------------*/
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/*! \brief Initialises the registers and mirror variables. */
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void GH_VIC_init(void);
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#ifdef SRC_INLINE
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#define SRC_INC 1
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#include "gh_vic.c"
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#undef SRC_INC
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _GH_VIC_H */
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/*----------------------------------------------------------------------------*/
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/* end of file */
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/*----------------------------------------------------------------------------*/
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