80 lines
3.9 KiB
C
80 lines
3.9 KiB
C
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/*!
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\file gd32f30x_fwdgt.h
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\brief definitions for the FWDGT
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2017-02-10, V1.0.1, firmware for GD32F30x
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*/
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#ifndef GD32F30X_FWDGT_H
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#define GD32F30X_FWDGT_H
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#include "gd32f30x.h"
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/* FWDGT definitions */
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#define FWDGT FWDGT_BASE
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/* registers definitions */
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#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
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#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */
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#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */
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#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */
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/* bits definitions */
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/* FWDGT_CTL */
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#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
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/* FWDGT_PSC */
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#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
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/* FWDGT_RLD */
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#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
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/* FWDGT_STAT */
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#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
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#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
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/* constants definitions */
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/* psc register value */
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#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
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#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
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#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
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#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
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#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
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#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
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#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
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#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
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/* control value */
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#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
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#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
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#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
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#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
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/* FWDGT timeout value */
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#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
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#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
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/* FWDGT flag definitions */
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#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
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#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
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/* function declarations */
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/* disable write access to FWDGT_PSC and FWDGT_RLD */
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void fwdgt_write_disable(void);
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/* start the free watchdog timer counter */
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void fwdgt_enable(void);
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/* reload the counter of FWDGT */
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void fwdgt_counter_reload(void);
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/* configure counter reload value, and prescaler divider value */
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ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
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/* get flag state of FWDGT */
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FlagStatus fwdgt_flag_get(uint16_t flag);
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#endif /* GD32F30X_FWDGT_H */
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