131 lines
5.5 KiB
ArmAsm
131 lines
5.5 KiB
ArmAsm
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/*
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* Copyright (c) 2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-05-05 jg1uaa the first version
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*/
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#include "../rtconfig.h"
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/* Interrupt Vectors */
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.section .isr_vector
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.thumb
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.align 0
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.long _estack // MSP default value
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.long Reset_Handler + 1 // 1: Reset
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.long default_handler + 1 // 2: NMI
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.long HardFault_Handler + 1 // 3: HardFault
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.long default_handler + 1 // 4: reserved
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.long default_handler + 1 // 5: reserved
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.long default_handler + 1 // 6: reserved
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.long default_handler + 1 // 7: reserved
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.long default_handler + 1 // 8: reserved
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.long default_handler + 1 // 9: reserved
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.long default_handler + 1 // 10: reserved
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.long default_handler + 1 // 11: SVCall
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.long default_handler + 1 // 12: reserved
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.long default_handler + 1 // 13: reserved
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.long PendSV_Handler + 1 // 14: PendSV
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.long SysTick_Handler + 1 // 15: SysTick
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.long default_handler + 1 // 16: External Interrupt(0)
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.long default_handler + 1 // 17: External Interrupt(1)
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.long default_handler + 1 // 18: External Interrupt(2)
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.long default_handler + 1 // 19: External Interrupt(3)
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.long default_handler + 1 // 20: External Interrupt(4)
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.long default_handler + 1 // 21: External Interrupt(5)
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.long default_handler + 1 // 22: External Interrupt(6)
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.long default_handler + 1 // 23: External Interrupt(7)
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.long default_handler + 1 // 24: External Interrupt(8)
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.long default_handler + 1 // 25: External Interrupt(9)
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.long default_handler + 1 // 26: External Interrupt(10)
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.long default_handler + 1 // 27: External Interrupt(11)
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.long default_handler + 1 // 28: External Interrupt(12)
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.long default_handler + 1 // 29: External Interrupt(13) C_CAN
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.long default_handler + 1 // 30: External Interrupt(14) SPI/SSP1
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.long default_handler + 1 // 31: External Interrupt(15) I2C
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.long default_handler + 1 // 32: External Interrupt(16) CT16B0
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.long default_handler + 1 // 33: External Interrupt(17) CT16B1
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.long default_handler + 1 // 34: External Interrupt(18) CT32B0
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.long default_handler + 1 // 35: External Interrupt(19) CT32B1
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.long default_handler + 1 // 36: External Interrupt(20) SPI/SSP0
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.long UART_IRQHandler + 1 // 37: External Interrupt(21) UART
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.long default_handler + 1 // 38: External Interrupt(22)
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.long default_handler + 1 // 39: External Interrupt(23)
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.long default_handler + 1 // 40: External Interrupt(24) ADC
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.long default_handler + 1 // 41: External Interrupt(25) WDT
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.long default_handler + 1 // 42: External Interrupt(26) BOD
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.long default_handler + 1 // 43: External Interrupt(27)
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.long default_handler + 1 // 44: External Interrupt(28) PIO_3
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.long default_handler + 1 // 45: External Interrupt(29) PIO_2
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.long default_handler + 1 // 46: External Interrupt(30) PIO_1
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.long default_handler + 1 // 47: External Interrupt(31) PIO_0
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.long default_handler + 1 // 48: External Interrupt(32)
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.long default_handler + 1 // 49: External Interrupt(33)
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.long default_handler + 1 // 50: External Interrupt(34)
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.long default_handler + 1 // 51: External Interrupt(35)
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.long default_handler + 1 // 52: External Interrupt(36)
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.long default_handler + 1 // 53: External Interrupt(37)
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.long default_handler + 1 // 54: External Interrupt(38)
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.long default_handler + 1 // 55: External Interrupt(39)
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.long default_handler + 1 // 56: External Interrupt(40)
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.long default_handler + 1 // 57: External Interrupt(41)
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.long default_handler + 1 // 58: External Interrupt(42)
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.long default_handler + 1 // 59: External Interrupt(43)
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.long default_handler + 1 // 60: External Interrupt(44)
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.long default_handler + 1 // 61: External Interrupt(45)
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.long default_handler + 1 // 62: External Interrupt(46)
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.long default_handler + 1 // 63: External Interrupt(47)
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/* startup */
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.section .text
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.thumb
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.align 0
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.global Reset_Handler
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Reset_Handler:
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/* initialize .data */
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data_init:
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ldr r1, =_sidata
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ldr r2, =_sdata
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ldr r3, =_edata
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cmp r2, r3
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beq bss_init
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data_loop:
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ldrb r0, [r1]
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add r1, r1, #1
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strb r0, [r2]
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add r2, r2, #1
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cmp r2, r3
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bne data_loop
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/* initialize .bss */
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bss_init:
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mov r0, #0
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ldr r2, =_sbss // sbss/ebss is 4byte aligned by link.lds
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ldr r3, =_ebss
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cmp r2, r3
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beq start_main
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bss_loop:
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str r0, [r2]
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add r2, r2, #4
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cmp r2, r3
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bne bss_loop
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/* launch main() */
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start_main:
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#ifdef RT_USING_USER_MAIN
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bl entry
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#else
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bl main
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#endif
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default_handler:
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die:
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b die
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.pool
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