263 lines
5.9 KiB
ArmAsm
263 lines
5.9 KiB
ArmAsm
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/* ------------------------------------------
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* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2016.05
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* \date 2014-07-15
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* \author Wayne Ren(Wei.Ren@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \ingroup ARC_HAL_STARTUP
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* \brief assembly part of startup process
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*/
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/**
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* \addtogroup ARC_HAL_STARTUP
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* @{
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*/
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/** @cond STARTUP_ASM */
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#define __ASSEMBLY__
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#include "embARC_BSP_config.h"
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#include "inc/arc/arc.h"
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.file "arc_startup.S"
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.weak _f_sdata /* start of small data, defined in link script */
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.weak init_hardware_hook /* app hardware init hook */
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.weak init_software_hook /* app software init hook */
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.extern board_main
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.extern exc_entry_table
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/* initial vector table */
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.section .init_vector, "a"
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.long _arc_reset
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.section .init_bootstrap, "ax"
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.global _arc_reset
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.global _start
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.align 4
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_start:
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_arc_reset:
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_arc_reset_stage1:
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kflag STATUS32_RESET_VALUE
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/* STAGE 1 */
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/* necessary hardware should be done first to speed up initialization
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1. system clk
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2. mem controller must be initialized before any access to external
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mem.
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3. others
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*/
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_arc_cache_init_start:
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lr r0, [AUX_BCR_D_CACHE]
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cmp r0, 2
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/* invalidate dcache */
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jle _arc_icache_init
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mov r0, 1
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sr r0, [AUX_DC_IVDC]
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sr r0, [AUX_DC_CTRL]
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_arc_icache_init:
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lr r0, [AUX_BCR_I_CACHE]
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cmp r0, 2
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jle _arc_cache_init_end
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/* invalidate icache */
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mov r0, 1
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sr r0, [AUX_IC_IVIC]
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nop_s
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nop_s
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nop_s
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sr r0, [AUX_IC_CTRL]
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_arc_cache_init_end:
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mov r0, init_hardware_hook
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cmp r0, 0
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jlne [r0]
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/* STAGE 2: init necessary registers */
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_arc_reset_stage2:
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mov r0, 0
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/* interrupt related init */
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sr r0, [AUX_IRQ_ACT]
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sr r0, [AUX_IRQ_CTRL]
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sr r0, [AUX_IRQ_HINT]
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/* use the new vector table to replace the old one */
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#if defined(ARC_FEATURE_SEC_PRESENT) && (SECURESHIELD_VERSION < 2)
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sr exc_entry_table, [AUX_INT_VECT_BASE_S]
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#else
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sr exc_entry_table, [AUX_INT_VECT_BASE]
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#endif
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/* init stack */
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#if ARC_FEATURE_RGF_BANKED_REGS >= 16 && ARC_FEATURE_RGF_BANKED_REGS > 1 && ARC_FEATURE_FIRQ == 1
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#if _STACKSIZE < 512
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#error "not enough stack size for irq and firq"
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#endif
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/* switch to register bank1 */
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lr r0, [AUX_STATUS32]
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bic r0, r0, 0x70000
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or r0, r0, 0x10000
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kflag r0
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/* set sp, gp, fp in bank1 */
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mov sp, _e_stack
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mov gp, _f_sdata
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mov fp, 0
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/* come back to bank0 */
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lr r0, [AUX_STATUS32]
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bic r0, r0, 0x70000
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kflag r0
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mov sp, _e_stack-256
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#else
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mov sp, _e_stack /* init stack pointer */
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#endif
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mov gp, _f_sdata /* init small-data base register */
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mov fp, 0 /* init fp register */
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_arc_reset_stage3:
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_s3_copy_text:
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mov r0, _f_text
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mov r1, _load_addr_text
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cmp r0, r1
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/* if load addr == run addr, no need to copy */
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jeq _s3_copy_rodata
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mov r3, _e_text
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_s3_copy_text_loop:
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ld.ab r2, [r1, 4]
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st.ab r2, [r0, 4]
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cmp r0, r3
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jlt _s3_copy_text_loop
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_s3_copy_rodata:
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mov r0, _f_rodata
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mov r1, _load_addr_rodata
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cmp r0, r1
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/* if load addr == run addr, no need to copy */
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jeq _s3_copy_data
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mov r3, _e_rodata
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_s3_copy_rodata_loop:
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ld.ab r2, [r1, 4]
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st.ab r2, [r0, 4]
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cmp r0, r3
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jlt _s3_copy_rodata_loop
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_s3_copy_data:
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mov r0, _f_data
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mov r1, _load_addr_data
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cmp r0, r1
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jeq _s3_clear_bss
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/* if load addr == run addr, no need to copy */
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mov r3, _e_data
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_s3_copy_data_loop:
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ld.ab r2, [r1, 4]
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st.ab r2, [r0, 4]
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cmp r0, r3
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jlt _s3_copy_data_loop
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_s3_clear_bss:
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mov r0, _f_bss
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mov r1, _e_bss
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cmp r0, r1
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jge _arc_reset_call_main
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mov r2, 0
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_s3_clear_bss_loop:
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st.ab r2, [r0, 4]
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cmp r0, r1
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jlt _s3_clear_bss_loop
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/* STAGE 3: go to main */
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_arc_reset_call_main:
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/* \todo add cpp init here */
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mov r0, init_software_hook
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cmp r0, 0
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jlne [r0]
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/* board level library init */
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/* early init of interrupt and exception */
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jl exc_int_init
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/* init cache */
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jl arc_cache_init
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#if defined(__MW__)
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jl _init
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#elif defined(__GNU__)
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jl __do_global_ctors_aux
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jl __do_init_array_aux
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#endif
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jl board_main /* board-level main */
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#if defined(__MW__)
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jl _fini
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#elif defined(__GNU__)
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jl __do_global_dtors_aux
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#endif
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.global _exit_loop
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.global _exit_halt
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.align 4
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_exit_halt:
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_exit_loop:
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flag 0x1
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nop
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nop
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nop
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b _exit_loop
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#if defined(__MW__)
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.global _init, _fini
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.section ".init",text
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_init:
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.cfa_bf _init
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push %blink
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.cfa_push {%blink}
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.section ".init$999999", text, 1, 2, check_text_align=0
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pop %blink
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.cfa_pop {%blink}
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j [%blink]
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.cfa_ef
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.section ".fini", text
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_fini:
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.cfa_bf _fini
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push %blink
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.cfa_push {%blink}
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.section ".fini$999999", text, 1, 2, check_text_align=0
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pop %blink
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.cfa_pop {%blink}
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j [%blink]
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.cfa_ef
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#endif
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/** @endcond */
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/** }@*/
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