202 lines
5.0 KiB
ArmAsm
202 lines
5.0 KiB
ArmAsm
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/* ------------------------------------------
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* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2016.05
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* \date 2014-07-15
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* \author Wayne Ren(Wei.Ren@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \ingroup ARC_HAL_EXCEPTION_CPU
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* \brief assembly part of exception and interrupt processing
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*/
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/**
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* \addtogroup ARC_HAL_EXCEPTION_CPU
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* @{
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*/
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/* function documentation */
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/**
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* \fn void exc_entry_cpu(void)
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* \brief default entry of CPU exceptions, such as TLB miss and swap.
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*
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* \fn void exc_entry_int(void)
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* \brief normal interrupt exception entry.
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* In default, all interrupt exceptions are installed with normal entry.
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* If FIRQ is required, exc_entry_firq should be the entry.
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*
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* \fn void exc_entry_firq(void)
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* \brief firq exception entry
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*/
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/** }@ */
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/** @cond EXCEPTION_ASM */
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#define __ASSEMBLY__
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#include "inc/arc/arc.h"
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#include "inc/arc/arc_asm_common.h"
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.file "arc_exc_asm.S"
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/* entry for cpu exception handling */
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.text
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.global exc_entry_cpu
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.weak exc_entry_cpu
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.align 4
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exc_entry_cpu:
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EXCEPTION_PROLOGUE
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mov r3, sp /* as exception handler's para(exc_frame) */
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/* exc_nest_count +1 */
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ld r0, [exc_nest_count]
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add r0, r0, 1
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st r0, [exc_nest_count]
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/* find the exception cause */
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lr r0, [AUX_ECR]
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lsr r0, r0, 16
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bmsk r0, r0, 7
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mov r1, exc_int_handler_table
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ld.as r2, [r1, r0]
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mov r0, r3
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jl [r2] /* jump to exception handler where interrupts are not allowed! */
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/* interrupts are not allowed */
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exc_return:
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/* exc_nest_count -1 */
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ld r0, [exc_nest_count]
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sub r0, r0, 1
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st r0, [exc_nest_count]
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EXCEPTION_EPILOGUE
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rtie
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/****** entry for normal interrupt exception handling ******/
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.global exc_entry_int
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.weak exc_entry_int
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.align 4
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exc_entry_int:
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clri /* disable interrupt */
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#if ARC_FEATURE_FIRQ == 1
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#if ARC_FEATURE_RGF_NUM_BANKS > 1
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lr r0, [AUX_IRQ_ACT] /* check whether it is P0 interrupt */
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btst r0, 0
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bnz exc_entry_firq
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#else
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PUSH r10
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lr r10, [AUX_IRQ_ACT]
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btst r10, 0
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POP r10
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bnz exc_entry_firq
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#endif
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#endif
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INTERRUPT_PROLOGUE /* save scratch regs, this will be affected */
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/* exc_nest_count +1 */
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ld r0, [exc_nest_count]
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add r0, r0, 1
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st r0, [exc_nest_count]
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lr r0, [AUX_IRQ_CAUSE]
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mov r1, exc_int_handler_table
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ld.as r2, [r1, r0] /* r2 = _kernel_exc_tbl + irqno *4 */
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/* for the case of software triggered interrupt */
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lr r3, [AUX_IRQ_HINT]
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cmp r3, r0
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bne.d irq_hint_handled
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xor r3, r3, r3
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sr r3, [AUX_IRQ_HINT]
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irq_hint_handled:
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seti /* enable higher priority interrupt */
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mov r0, sp
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jl [r2] /* jump to interrupt handler */
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/* no interrupts are allowed from here */
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int_return:
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clri /* disable interrupt */
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/* exc_nest_count -1 */
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ld r0, [exc_nest_count]
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sub r0, r0, 1
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st r0, [exc_nest_count]
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INTERRUPT_EPILOGUE
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rtie
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/****** entry for fast irq exception handling ******/
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.global exc_entry_firq
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.weak exc_entry_firq
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.align 4
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exc_entry_firq:
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clri /* disable interrupt */
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SAVE_FIQ_EXC_REGS
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/* exc_nest_count +1 */
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ld r0, [exc_nest_count]
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add r0, r0, 1
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st r0, [exc_nest_count]
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lr r0, [AUX_IRQ_CAUSE]
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mov r1, exc_int_handler_table
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ld.as r2, [r1, r0] /* r2 = _kernel_exc_tbl + irqno *4 */
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/* for the case of software triggered interrupt */
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lr r3, [AUX_IRQ_HINT]
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cmp r3, r0
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bne.d firq_hint_handled
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xor r3, r3, r3
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sr r3, [AUX_IRQ_HINT]
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firq_hint_handled:
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jl [r2] /* jump to interrupt handler */
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/* no interrupts are allowed from here */
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firq_return:
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/* exc_nest_count -1 */
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ld r0, [exc_nest_count]
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sub r0, r0, 1
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st r0, [exc_nest_count]
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RESTORE_FIQ_EXC_REGS
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rtie
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/** @endcond */
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