132 lines
2.0 KiB
ArmAsm
132 lines
2.0 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024/01/11 flyingcys The first version
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*/
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#include "riscv-virt.h"
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.org 0
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.section .vectors, "ax"
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.globl _start
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.type _start,@function
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_start:
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.cfi_startproc
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.cfi_undefined ra
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.option push
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.option norelax
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// la gp, __global_pointer$
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.option pop
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// Continue primary hart
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csrr a0, mhartid
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li a1, PRIM_HART
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bne a0, a1, secondary
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10, 0
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li x11, 0
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li x12, 0
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li x13, 0
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li x14, 0
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li x15, 0
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li x16, 0
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li x17, 0
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li x18, 0
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li x19, 0
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li x20, 0
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li x21, 0
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li x22, 0
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li x23, 0
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li x24, 0
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li x25, 0
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li x26, 0
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li x27, 0
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li x28, 0
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li x29, 0
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li x30, 0
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li x31, 0
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// enable interrupt
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// li x3, 0x880
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// csrw mie, x3
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csrw mie, 0
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csrw mip, 0
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la t0, trap_entry
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csrw mtvec, t0
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#ifndef RISCV_QEMU
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// invalidate all memory for BTB,BHT,DCACHE,ICACHE
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li x3, 0x30013
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csrs mcor, x3
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// enable ICACHE,DCACHE,BHT,BTB,RAS,WA
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li x3, 0x7f
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csrs mhcr, x3
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// enable data_cache_prefetch, amr
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li x3, 0x610c
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csrs mhint, x3 #mhint
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#endif
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# enable fp
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li x3, 0x1 << 13
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csrs mstatus, x3
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// Primary hart
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la sp, _stack_top
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// Load data section
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la a0, _data_lma
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la a1, _data
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la a2, _edata
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bgeu a1, a2, 2f
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1:
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LOAD t0, (a0)
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STOR t0, (a1)
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addi a0, a0, REGSIZE
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addi a1, a1, REGSIZE
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bltu a1, a2, 1b
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2:
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// Clear bss section
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la a0, _bss
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la a1, _ebss
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bgeu a0, a1, 2f
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1:
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// reduce branch time, be sure about bss alignment in linker script
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STOR zero, 0x00 (a0)
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STOR zero, 0x08 (a0)
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STOR zero, 0x10 (a0)
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STOR zero, 0x18 (a0)
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STOR zero, 0x20 (a0)
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STOR zero, 0x28 (a0)
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STOR zero, 0x30 (a0)
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STOR zero, 0x38 (a0)
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addi a0, a0, REGSIZE * 8
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bltu a0, a1, 1b
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2:
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// argc, argv, envp is 0
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li a0, 0
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li a1, 0
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li a2, 0
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jal entry
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1:
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wfi
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j 1b
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secondary:
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// TODO: Multicore is not supported
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wfi
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j secondary
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.cfi_endproc
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