142 lines
3.4 KiB
C
142 lines
3.4 KiB
C
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/*
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* ===========================================================================================
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*
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* Filename: sunxi_hal_spi.h
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*
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* Description: SPI HAL definition.
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*
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* Version: Melis3.0
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* Create: 2020-04-08 11:11:56
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* Revision: none
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* Compiler: GCC:version 9.2.1
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*
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* Author: bantao@allwinnertech.com
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* Organization: SWC-BPD
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* Last Modified: 2020-04-08 16:02:11
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*
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* ===========================================================================================
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*/
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#ifndef SUNXI_IR_RX_H
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#define SUNXI_IR_RX_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "sunxi_hal_common.h"
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#include <hal_gpio.h>
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#include <hal_sem.h>
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#include <hal_clk.h>
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#define SUNXI_IRADC_PBASE 0X07040000 /* 0x34 */
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#define SUNXI_IRQ_IRADC 155
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#define IRADC_PIN GPIO_PH0
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#define IR_MUXSEL 4
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#define IR_DRVSEL 2
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/* Registers */
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#define IR_CTRL_REG (0x00) /* IR Control */
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#define IR_RXCFG_REG (0x10) /* Rx Config */
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#define IR_RXDAT_REG (0x20) /* Rx Data */
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#define IR_RXINTE_REG (0x2C) /* Rx Interrupt Enable */
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#define IR_RXINTS_REG (0x30) /* Rx Interrupt Status */
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#define IR_SPLCFG_REG (0x34) /* IR Sample Config */
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#define IR_FIFO_SIZE (64) /* 64Bytes */
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#define IR_SIMPLE_UNIT (21000) /* simple in ns */
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#define IR_CLK (24000000) /* 24Mhz */
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#define IR_SAMPLE_DEV (0x3<<0) /* 24MHz/512 =46875Hz (~21us) */
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/* Active Threshold (0+1)*128clock*21us = 2.6ms */
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#define IR_ACTIVE_T ((0&0xff)<<16)
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/* Filter Threshold = 16*21us = 336us < 500us */
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#define IR_RXFILT_VAL (((16)&0x3f)<<2)
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/* Filter Threshold = 22*21us = 336us < 500us */
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#define IR_RXFILT_VAL_RC5 (((22)&0x3f)<<2)
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/* Idle Threshold = (5+1)*128clock*21us = 16ms > 9ms */
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#define IR_RXIDLE_VAL (((5)&0xff)<<8)
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/* Active Threshold (0+1)*128clock*21us = 2.6ms */
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#define IR_ACTIVE_T_SAMPLE ((16&0xff)<<16)
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#define IR_ACTIVE_T_C (1<<23) /* Active Threshold */
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#define IR_CIR_MODE (0x3<<4) /* CIR mode enable */
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#define IR_ENTIRE_ENABLE (0x3<<0) /* IR entire enable */
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#define IR_FIFO_20 (((20)-1)<<8)
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#define IR_IRQ_STATUS ((0x1<<4)|0x3)
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#define IR_BOTH_PULSE (0x1 << 6)
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#define IR_LOW_PULSE (0x2 << 6)
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#define IR_HIGH_PULSE (0x3 << 6)
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/*Bit Definition of IR_RXINTS_REG Register*/
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#define IR_RXINTS_RXOF (0x1<<0) /* Rx FIFO Overflow */
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#define IR_RXINTS_RXPE (0x1<<1) /* Rx Packet End */
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#define IR_RXINTS_RXDA (0x1<<4) /* Rx FIFO Data Available */
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enum ir_mode {
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CIR_MODE_ENABLE,
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IR_MODULE_ENABLE,
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IR_BOTH_PULSE_MODE, /* new feature to avoid noisy */
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IR_LOW_PULSE_MODE,
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IR_HIGH_PULSE_MODE,
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};
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enum ir_sample_config {
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IR_SAMPLE_REG_CLEAR,
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IR_CLK_SAMPLE,
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IR_FILTER_TH_NEC,
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IR_FILTER_TH_RC5,
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IR_IDLE_TH,
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IR_ACTIVE_TH,
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IR_ACTIVE_TH_SAMPLE,
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};
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enum ir_irq_config {
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IR_IRQ_STATUS_CLEAR,
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IR_IRQ_ENABLE,
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IR_IRQ_FIFO_SIZE,
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};
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typedef enum
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{
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IR_PIN_ERR = -3,
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IR_CLK_ERR = -2,
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IR_IRQ_ERR = -1,
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IR_OK = 0,
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} hal_ir_status_t;
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typedef int (*ir_callback_t)(uint32_t data_type, uint32_t data);
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typedef struct sunxi_ir
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{
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uint16_t irq_num;
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uint32_t reg_base;
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gpio_pin_t pin;
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uint8_t pin_mux;
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uint8_t pin_drv;
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ir_callback_t callback;
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} hal_ir_t;
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int hal_ir_register_callback(ir_callback_t callback);
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int hal_ir_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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