375 lines
12 KiB
C
375 lines
12 KiB
C
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/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SUNXI_HAL_GETH_H__
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#define __SUNXI_HAL_GETH_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <rtthread.h>
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#include <netif/ethernetif.h>
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#include <sunxi_hal_common.h>
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#include <sunxi_hal_phy.h>
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#include <interrupt.h>
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#include <hal_gpio.h>
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#define CONFIG_DRIVERS_GETH_DEBUG
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#ifdef CONFIG_DRIVERS_GETH_DEBUG
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#define GETH_INFO(fmt, arg...) printf("GPIO : %s()%d "fmt, __func__, __LINE__, ##arg)
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#define GETH_ERR(fmt, arg...) printf("GPIO : %s()%d "fmt, __func__, __LINE__, ##arg)
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#else
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#define GETH_INFO(fmt, arg...) do {}while(0)
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#define GETH_ERR(fmt, arg...) do {}while(0)
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#endif
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/* Base config for geth */
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#define IOBASE 0x04500000
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#define PHY_CLK_REG (0x03000000 + 0x30)
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#define CCMU_BASE 0x02001000
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#define CCMU_GETH_CLK_REG 0x097c
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#define CCMU_GETH_RST_BIT 16
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#define CCMU_GETH_GATING_BIT 0
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#define CCMU_EPHY_CLK_REG 0x0970
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#define CCMU_EPHY_SCLK_GATING_BIT 31
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#define CCMU_EPHY_PLL_PERI0_GATING_BIT 30
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//#define DISABLE_AUTONEG
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#define CONFIG_HARD_CHECKSUM
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#define USE_EPHY25M
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#define GETH_IRQ_NUM 62
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/* Geth register list */
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#define GETH_BASIC_CTL0 0x00
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#define GETH_BASIC_CTL1 0x04
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#define GETH_INT_STA 0x08
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#define GETH_INT_EN 0x0C
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#define GETH_TX_CTL0 0x10
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#define GETH_TX_CTL1 0x14
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#define GETH_TX_FLOW_CTL 0x1C
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#define GETH_TX_DESC_LIST 0x20
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#define GETH_RX_CTL0 0x24
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#define GETH_RX_CTL1 0x28
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#define GETH_RX_DESC_LIST 0x34
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#define GETH_RX_FRM_FLT 0x38
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#define GETH_RX_HASH0 0x40
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#define GETH_RX_HASH1 0x44
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#define GETH_MDIO_ADDR 0x48
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#define GETH_MDIO_DATA 0x4C
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#define GETH_ADDR_HI(reg) (0x50 + ((reg) << 3))
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#define GETH_ADDR_LO(reg) (0x54 + ((reg) << 3))
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#define GETH_TX_DMA_STA 0xB0
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#define GETH_TX_CUR_DESC 0xB4
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#define GETH_TX_CUR_BUF 0xB8
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#define GETH_RX_DMA_STA 0xC0
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#define GETH_RX_CUR_DESC 0xC4
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#define GETH_RX_CUR_BUF 0xC8
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#define GETH_RGMII_STA 0xD0
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#define MII_BUSY 0x00000001
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#define MII_WRITE 0x00000002
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#define CTL0_DM 0x01
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#define CTL0_LM 0x02
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#define CTL0_SPEED 0x04
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#define BURST_LEN 0x3F000000
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#define RX_TX_PRI 0x02
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#define SOFT_RST 0x01
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#define TX_FLUSH 0x01
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#define TX_MD 0x02
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#define TX_NEXT_FRM 0x04
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#define TX_TH 0x0700
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#define RX_FLUSH 0x01
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#define RX_MD 0x02
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#define RX_RUNT_FRM 0x04
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#define RX_ERR_FRM 0x08
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#define RX_TH 0x0030
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#define STRIP_FCS 0x10000000
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#define TX_INT 0x00000001
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#define TX_STOP_INT 0x00000002
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#define TX_UA_INT 0x00000004
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#define TX_TOUT_INT 0x00000008
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#define TX_UNF_INT 0x00000010
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#define TX_EARLY_INT 0x00000020
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#define RX_INT 0x00000100
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#define RX_UA_INT 0x00000200
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#define RX_STOP_INT 0x00000400
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#define RX_TOUT_INT 0x00000800
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#define RX_OVF_INT 0x00001000
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#define RX_EARLY_INT 0x00002000
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#define LINK_STA_INT 0x00010000
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/* PHY address */
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#define PHY_DM 0x0010
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#define PHY_AUTO_NEG 0x0020
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#define PHY_POWERDOWN 0x0080
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#define PHY_NEG_EN 0x1000
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#define EXT_PHY 0
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#define INT_PHY 1
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#define MAX_ADDR_LEN 6
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#define ENET_FRAME_MAX_FRAMELEN 1518
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#define DMA_DESC_RX_NUM 64
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#define DMA_DESC_TX_NUM 64
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#define DMA_MEM_ALIGN_SIZE 2048
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#define SYS_PAGE_SIZE (4096U)
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#define TX_BUFFER_INDEX_NUM (6)
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#define RX_BUFFER_INDEX_NUM (6)
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#define TX_BD_INDEX_NUM (1)
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#define RX_BD_INDEX_NUM (1)
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#define PBUF_MAX_BUFF_SIZE 1514
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#define SZ_2K 0x00000800
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#define MAX_BUF_SZ (SZ_2K - 1)
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#define circ_inc(n, s) (((n) + 1) % (s))
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#define u8 uint8_t
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#define u16 uint16_t
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#define u32 uint32_t
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typedef enum rx_frame_status {
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good_frame = 0,
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discard_frame = 1,
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csum_none = 2,
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llc_snap = 4,
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} hal_geth_rx_frame_status_t;
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typedef union {
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struct {
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/* TDES0 */
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u32 deferred:1; /* Deferred bit (only half-duplex) */
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u32 under_err:1; /* Underflow error */
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u32 ex_deferral:1; /* Excessive deferral */
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u32 coll_cnt:4; /* Collision count */
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u32 vlan_tag:1; /* VLAN Frame */
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u32 ex_coll:1; /* Excessive collision */
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u32 late_coll:1; /* Late collision */
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u32 no_carr:1; /* No carrier */
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u32 loss_carr:1; /* Loss of collision */
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u32 ipdat_err:1; /* IP payload error */
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u32 frm_flu:1; /* Frame flushed */
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u32 jab_timeout:1; /* Jabber timeout */
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u32 err_sum:1; /* Error summary */
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u32 iphead_err:1; /* IP header error */
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u32 ttss:1; /* Transmit time stamp status */
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u32 reserved0:13;
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u32 own:1; /* Own bit. CPU:0, DMA:1 */
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} tx;
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struct {
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/* RDES0 */
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u32 chsum_err:1; /* Payload checksum error */
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u32 crc_err:1; /* CRC error */
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u32 dribbling:1; /* Dribble bit error */
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u32 mii_err:1; /* Received error (bit3) */
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u32 recv_wt:1; /* Received watchdog timeout */
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u32 frm_type:1; /* Frame type */
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u32 late_coll:1; /* Late Collision */
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u32 ipch_err:1; /* IPv header checksum error (bit7) */
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u32 last_desc:1; /* Laset descriptor */
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u32 first_desc:1; /* First descriptor */
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u32 vlan_tag:1; /* VLAN Tag */
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u32 over_err:1; /* Overflow error (bit11) */
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u32 len_err:1; /* Length error */
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u32 sou_filter:1; /* Source address filter fail */
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u32 desc_err:1; /* Descriptor error */
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u32 err_sum:1; /* Error summary (bit15) */
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u32 frm_len:14; /* Frame length */
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u32 des_filter:1; /* Destination address filter fail */
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u32 own:1; /* Own bit. CPU:0, DMA:1 */
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#define RX_PKT_OK 0x7FFFB77C
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#define RX_LEN 0x3FFF0000
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} rx;
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u32 all;
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} desc0_u;
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typedef union {
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struct {
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/* TDES1 */
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u32 buf1_size:11; /* Transmit buffer1 size */
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u32 buf2_size:11; /* Transmit buffer2 size */
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u32 ttse:1; /* Transmit time stamp enable */
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u32 dis_pad:1; /* Disable pad (bit23) */
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u32 adr_chain:1; /* Second address chained */
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u32 end_ring:1; /* Transmit end of ring */
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u32 crc_dis:1; /* Disable CRC */
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u32 cic:2; /* Checksum insertion control (bit27:28) */
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u32 first_sg:1; /* First Segment */
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u32 last_seg:1; /* Last Segment */
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u32 interrupt:1; /* Interrupt on completion */
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} tx;
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struct {
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/* RDES1 */
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u32 buf1_size:11; /* Received buffer1 size */
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u32 buf2_size:11; /* Received buffer2 size */
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u32 reserved1:2;
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u32 adr_chain:1; /* Second address chained */
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u32 end_ring:1; /* Received end of ring */
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u32 reserved2:5;
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u32 dis_ic:1; /* Disable interrupt on completion */
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} rx;
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u32 all;
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} desc1_u;
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typedef struct dma_desc {
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desc0_u desc0;
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desc1_u desc1;
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u32 desc2;
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u32 desc3;
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u32 resever0;
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u32 resever1;
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u32 resever2;
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u32 resever3;
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u32 resever4;
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u32 resever5;
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u32 resever6;
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u32 resever7;
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u32 resever8;
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u32 resever9;
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u32 resever10;
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u32 resever11;
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} hal_geth_dma_desc_t;
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typedef struct geth_buffer_config
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{
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hal_geth_dma_desc_t *dma_desc_tx;
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hal_geth_dma_desc_t *dma_desc_rx;
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hal_geth_dma_desc_t *phy_dma_desc_tx;
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hal_geth_dma_desc_t *phy_dma_desc_rx;
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void *tx_buff_addr;
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void *rx_buff_addr;
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void *phy_tx_buff_addr;
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void *phy_rx_buff_addr;
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} geth_buffer_config_t;
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struct geth_device {
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/* inherit from ethernet device */
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struct eth_device parent;
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/* interface address info, hw address */
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uint8_t dev_addr[MAX_ADDR_LEN];
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/* ethernet device base address */
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unsigned long iobase;
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/* phy mode */
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phy_interface_t phy_interface;
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rt_bool_t phy_link_status;
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geth_buffer_config_t get_buffer_config;
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uint32_t used_type;
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uint32_t tx_delay;
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uint32_t rx_delay;
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};
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typedef struct geth_priv {
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struct hal_gmac_dma_desc_t *dma_desc_tx;
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struct hal_gmac_dma_desc_t *dma_desc_rx;
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char *rx_handle_buf;
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int32_t base;
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int32_t phy_tpye;
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int32_t phy_interface;
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} hal_geth_priv_data_t;
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typedef struct sunxi_hal_driver_geth {
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rt_err_t (*initialize)(rt_device_t dev);
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void (*uninitialize)(rt_device_t dev);
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int32_t (*get_mac_address)(const unsigned char *addr);
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int32_t (*set_mac_address)(unsigned char *addr);
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int32_t (*set_address_filter)(void);
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rt_err_t (*send)(rt_device_t dev, struct pbuf *p);
|
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|
|
struct pbuf* (*recv)(rt_device_t dev);
|
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|
//int32_t (*phy_read)(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
|
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|
|
//int32_t (*phy_write)(uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
|
|||
|
|
} const sunxi_hal_driver_geth_t;
|
|||
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|
|
|||
|
|
void random_ether_addr(u8 *addr);
|
|||
|
|
void geth_set_link_mode(unsigned long iobase, int duplex, int speed);
|
|||
|
|
void geth_mac_loopback(unsigned long iobase, int enable);
|
|||
|
|
void geth_start_tx(unsigned long iobase);
|
|||
|
|
void geth_stop_tx(unsigned long iobase);
|
|||
|
|
void geth_start_rx(unsigned long iobase);
|
|||
|
|
void geth_stop_rx(unsigned long iobase);
|
|||
|
|
uint32_t geth_mac_reset(unsigned long iobase);
|
|||
|
|
void geth_mac_init(unsigned long iobase);
|
|||
|
|
void geth_set_filter(unsigned long iobase);
|
|||
|
|
void geth_set_mac_addr(unsigned long iobase, unsigned char *addr, int index);
|
|||
|
|
void geth_mac_enable(unsigned long iobase);
|
|||
|
|
void geth_mac_disable(unsigned long iobase);
|
|||
|
|
void geth_tx_poll(unsigned long iobase);
|
|||
|
|
void geth_rx_poll(unsigned long iobase);
|
|||
|
|
void geth_flush_tx(unsigned long iobase);
|
|||
|
|
void geth_rx_int_enable(unsigned long iobase);
|
|||
|
|
void geth_rx_int_disable(unsigned long iobase);
|
|||
|
|
void geth_tx_int_enable(unsigned long iobase);
|
|||
|
|
void geth_tx_int_disable(unsigned long iobase);
|
|||
|
|
void geth_all_int_disable(unsigned long iobase);
|
|||
|
|
void geth_clk_enable(uint32_t used_type,uint32_t phy_interface,uint32_t tx_delay,uint32_t rx_delay);
|
|||
|
|
void geth_clk_disable(void);
|
|||
|
|
uint32_t geth_mdio_read(unsigned long iobase, int phy_addr, u8 reg);
|
|||
|
|
uint32_t geth_mdio_write(unsigned long iobase, int phy_addr, u8 reg, u16 data);
|
|||
|
|
void rt_geth_driver_init(void);
|
|||
|
|
void geth_loopback_enable(unsigned long iobase);
|
|||
|
|
void geth_loopback_disable(unsigned long iobase);
|
|||
|
|
|
|||
|
|
|
|||
|
|
#ifdef __cplusplus
|
|||
|
|
}
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#endif /* __SUNXI_HAL_GETH_H__ */
|