422 lines
12 KiB
C
422 lines
12 KiB
C
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/*
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* Copyright (c) 2020-2020, BLUETRUM Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "ab32vgx.h"
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#ifndef ALIGN
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#define ALIGN(n) __attribute__((aligned(n)))
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#endif // ALIGN
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typedef struct _sys_t {
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uint8_t cnt_1us; //delay 1us cnt
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uint8_t main_start; //Main是否已启动
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uint8_t clk_sel; //system clock select
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uint8_t sys_clk;
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// uint8_t aupll_type; //区分AUPLL的频率
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uint16_t rand_seed;
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uint32_t uart0baud; //UART0BAUD
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} sys_t;
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const uint8_t sysclk_sel_tbl[] = {
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OSCDIV_2M, //SYS_2M
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PLL0DIV_12M, //SYS_12M
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OSCDIV_13M, //SYS_13M
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PLL0DIV_24M, //SYS_24M
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OSCDIV_26M, //SYS_26M
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PLL0DIV_30M, //SYS_30M
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PLL0DIV_48M, //SYS_48M
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PLL0DIV_60M, //SYS_60M
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PLL0DIV_80M, //SYS_80M
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PLL0DIV_120M, //SYS_120M
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};
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const uint8_t sysclk_index[] = {
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2,
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12,
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13,
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24,
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26,
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30,
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48,
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60,
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80,
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120,
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};
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sys_t sys = {0};
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void my_printf(const char *format, ...);
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static void delay_us(uint16_t nus)
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{
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int i;
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for (i = 0; i < nus*10; i++) {
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asm("nop");
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}
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}
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uint8_t get_clksel_val(uint8_t val)
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{
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return sysclk_sel_tbl[val];
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}
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uint8_t get_cur_sysclk(void)
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{
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return sys.sys_clk;
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}
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uint32_t get_sysclk_nhz(void)
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{
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return sysclk_index[sys.sys_clk] * 1000000;
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}
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////AT(.com_text.set_flash_safety)
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//static ALWAYS_INLINE void set_flash_safety(uint32_t sys_clk)
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//{
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// SPI0CON |= BIT(10);
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// if (sys_clk > SYS_48M) {
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// SPI0CON |= BIT(3); //2bit mode
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// spiflash_init(0x3b, 1); //dummy = 1
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// } else {
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// SPI0CON &= ~BIT(3); //2bit mode
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// spiflash_init(0x0b, 1); //dummy = 0
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// }
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//}
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uint8_t get_sd_rate(void)
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{
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return 0; //unit: M
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}
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uint8_t set_sd_baud(uint8_t sd_rate)
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{
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uint8_t sd0baud=0;
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uint8_t sys_clk=0;
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if(sd_rate > 14){//不支持超过14M
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return 0;
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}
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if (sys.sys_clk <= SYSCLK_26M) {
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sys_clk=26;
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}else if (sys.sys_clk == SYSCLK_48M) {
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sys_clk=48;
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} else if (sys.sys_clk <= SYSCLK_60M) {
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sys_clk=52;
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} else if (sys.sys_clk == SYSCLK_80M) {
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sys_clk=80;
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} else if (sys.sys_clk <= SYSCLK_120M) {
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sys_clk=120;
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}
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sd0baud = sys_clk/sd_rate-1;
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if(sys_clk%sd_rate*2/sd_rate) {
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sd0baud=sd0baud+1;
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}
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return sd0baud;
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}
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void update_sd0baud(void)
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{
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if (!(SD0CON & BIT(0))) {
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return;
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}
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uint8_t sd_rate=get_sd_rate();
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if(sd_rate){
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uint8_t sd0baud=set_sd_baud(sd_rate);
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if(sd0baud){
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SD0BAUD=sd0baud;
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return ;
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}
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}
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if (sys.sys_clk <= SYSCLK_30M) {
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SD0BAUD = 1;
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} else if (sys.sys_clk <= SYSCLK_60M) {
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SD0BAUD = 3;
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} else if (sys.sys_clk == SYSCLK_80M) {
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SD0BAUD = 5;
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} else if (sys.sys_clk <= SYSCLK_120M) {
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SD0BAUD = 9;
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}
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}
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uint8_t sysclk_update_baud(uint8_t baud)
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{
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uint8_t sd_rate=get_sd_rate();
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if(baud>20||!sd_rate) {
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if (sys.sys_clk == SYSCLK_120M) {
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return ((uint16_t)(baud + 1) * 25 / 10 - 1);
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} else if (sys.sys_clk >= SYSCLK_80M) {
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return ((baud + 1) * 2 - 1);
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} else if (sys.sys_clk <= SYSCLK_30M) {
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return (((baud + 1) >> 1) - 1);
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}
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} else if (sd_rate){
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return set_sd_baud(sd_rate);
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}
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return baud;
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}
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//客户可能用到UART0(使用26M时钟源)做通信,这里可选设置系统时钟时不改波特率
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WEAK void update_uart0baud_in_sysclk(uint32_t uart_baud)
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{
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if(UART0CON & BIT(0)) {
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while (!(UART0CON & BIT(8)));
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}
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UART0BAUD = (uart_baud << 16) | uart_baud;
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}
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void set_sys_uart0baud(uint32_t baud)
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{
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sys.uart0baud = baud;
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}
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//切系统时钟前，先设置模块时钟分频较大值，保证模块不会超频的情况
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void set_peripherals_clkdiv_safety(void)
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{
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uint32_t clkcon3 = CLKCON3;
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uint32_t clkcon2 = CLKCON2;
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//src clkdiv
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clkcon3 &= ~0xf0; //reset src clkdiv
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clkcon3 |= (1 << 4); //src clk = sys_clk / (n+1)
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//sbcenc硬件要小于48M
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clkcon3 &= ~(0x0f << 12); //reset sbcenc clkdiv
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clkcon3 |= (2 << 12); //src clk = sys_clk / (n+1)
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//aec ram硬件要小于50M
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clkcon3 &= ~0x0f; //reset aec clkdiv
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clkcon3 &= ~(0x0f << 19); //reset plc clkdiv
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clkcon3 &= ~(0x0f << 23); //reset cvsd clkdiv
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clkcon3 |= 0x02; //aec clk = sys_clk / (n+1)
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clkcon3 |= (2 << 19); //plc clk = sys_clk / (n+1)
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clkcon3 |= (2 << 23); //cvsd clk = sys_clk / (n+1)
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//audec硬件要小于48M
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clkcon2 &= ~(0x0f << 13); //reset audec clkdiv
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clkcon2 |= (2 << 13); //audec clk = sys_clk / (n+1)
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CLKCON3 = clkcon3;
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CLKCON2 = clkcon2;
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}
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//根据实际系统时钟，设置合适的模块时钟分频
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void set_peripherals_clkdiv(void)
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{
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uint32_t clkcon3 = CLKCON3;
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uint32_t clkcon2 = CLKCON2;
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uint32_t clkdiv;
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uint8_t sys_clk = sys.sys_clk;
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//src clkdiv
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clkcon3 &= ~0xf0; //reset src clkdiv
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if (sys_clk > SYSCLK_80M) {
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clkcon3 |= (1 << 4); //src clk = sys_clk / (n+1)
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}
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//sbcec硬件要小于48M
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clkcon3 &= ~(0x0f << 12);
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if (sys_clk > SYSCLK_80M) {
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clkcon3 |= (2 << 12);
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} else if (sys_clk >= SYSCLK_60M) {
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clkcon3 |= (1 << 12);
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}
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//aec ram硬件要小于50M
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clkcon3 &= ~0x0f; //reset aec clkdiv
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clkcon3 &= ~(0x0f << 19); //reset plc clkdiv
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clkcon3 &= ~(0x0f << 23); //reset cvsd clkdiv
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if (sys_clk > SYSCLK_80M) {
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clkdiv = 2;
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} else if (sys_clk >= SYSCLK_60M) {
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clkdiv = 1;
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} else {
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clkdiv = 0;
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}
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clkcon3 |= clkdiv; //aec clk = sys_clk / (n+1)
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clkcon3 |= (clkdiv << 19); //plc clk = sys_clk / (n+1)
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clkcon3 |= (clkdiv << 23); //cvsd clk = sys_clk / (n+1)
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//audec硬件要小于48M
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clkcon2 &= ~(0x0f << 13); //reset audec clkdiv
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if (sys_clk > SYSCLK_80M) {
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clkdiv = 2;
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} else if (sys_clk >= SYSCLK_60M) {
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clkdiv = 1;
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} else {
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clkdiv = 0;
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}
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clkcon2 |= (clkdiv << 13); //audec clk = sys_clk / (n+1)
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CLKCON3 = clkcon3;
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CLKCON2 = clkcon2;
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// if (sys_clk <= SYS_48M) {
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// PWRCON0 = (PWRCON0 & ~0xf) | (sys_trim.vddcore); //VDDCORE减一档
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// }
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// vddcore_other_offset();
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}
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ALIGN(512) //注意：超过512byte时，要用lock cache
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static void set_sysclk_do(uint32_t sys_clk, uint32_t clk_sel, uint32_t spll_div, uint32_t spi_baud, uint32_t spi1baud)
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{
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uint32_t cpu_ie;
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cpu_ie = PICCON & BIT(0);
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PICCONCLR = BIT(0); //关中断，切换系统时钟
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set_peripherals_clkdiv_safety();
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CLKCON0 &= ~(BIT(2) | BIT(3)); //sysclk sel rc2m
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CLKCON2 &= ~(0x1f << 8); //reset spll div
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if(clk_sel <= PLL0DIV_120M) {
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//sys_clk来源PLL0的分频配置
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CLKCON0 &= ~(BIT(4) | BIT(5) | BIT(6)); //sys_pll select pll0out
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if (PLL0DIV != (240 * 65536 / 26)) {
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PLL0DIV = 240 * 65536 / 26; //pll: 240M, XOSC: 26M
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PLL0CON &= ~(BIT(3) | BIT(4) | BIT(5));
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PLL0CON |= BIT(3); //Select PLL/VCO frequency band (PLL大于206M vcos = 0x01, 否则为0)
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PLL0CON |= BIT(20); //update pll0div to pll0_clk
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CLKCON3 &= ~(7 << 16);
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CLKCON3 |= (4 << 16); //USB CLK 48M
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}
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} else if (clk_sel <= OSCDIV_26M) {
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//sys_clk来源于XOSC26M时钟分频, 无USB时关闭PLL0
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// if (!is_usb_support()) {
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// PLL0CON &= ~BIT(18);
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// PLL0CON &= ~(BIT(12) | BIT(6)); //close pll0
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// }
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CLKCON0 &= ~(BIT(4) | BIT(5) | BIT(6));
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CLKCON0 |= BIT(6); //spll select xosc26m_clk
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}
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CLKCON2 |= (spll_div << 8);
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CLKCON0 |= BIT(3); //sysclk sel spll
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SPI0BAUD = spi_baud;
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if (CLKGAT1 & BIT(12)) {
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SPI1BAUD = spi1baud;
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}
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// if (spiflash_speed_up_en()) {
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// set_flash_safety(sys_clk);
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// }
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PICCON |= cpu_ie;
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}
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void set_sysclk(uint32_t sys_clk)
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{
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uint32_t uart_baud, spll_div = 0, spi_baud = 0, spi1baud;
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uint8_t cnt_1us, clk_sel;
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clk_sel = get_clksel_val(sys_clk);
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if(sys.clk_sel == clk_sel) {
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return;
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}
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// if (sys_clk > SYSCLK_48M) {
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// PWRCON0 = (PWRCON0 & ~0xf) | (sys_trim.vddcore + 1); //VDDCORE加一档
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// }
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// vddcore_other_offset();
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// printf("%s: %d, %d\n", __func__, sys_clk, clk_sel);
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switch (sys_clk) {
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case SYSCLK_12M:
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spll_div = 19; //pll0 240M
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cnt_1us = 1;
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spi_baud = 0;
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spi1baud = 0;
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break;
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case SYSCLK_24M:
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spll_div = 9; //pll0 240M
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cnt_1us = 2;
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spi_baud = 0;
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spi1baud = 1;
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break;
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|
|
case SYSCLK_30M:
|
|||
|
|
spll_div = 7; //pll0 240M
|
|||
|
|
cnt_1us = 3;
|
|||
|
|
spi_baud = 1; //Baud Rate =Fsys clock / (SPI_BAUD+1)
|
|||
|
|
spi1baud = 1;
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case SYSCLK_48M:
|
|||
|
|
spll_div = 4; //pll0 240M
|
|||
|
|
cnt_1us = 4;
|
|||
|
|
spi_baud = 1; //Baud Rate =Fsys clock / (SPI_BAUD+1)
|
|||
|
|
spi1baud = 3;
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case SYSCLK_60M:
|
|||
|
|
spll_div = 3; //pll0 240M
|
|||
|
|
cnt_1us = 5;
|
|||
|
|
spi_baud = 2; //Baud Rate =Fsys clock / (SPI_BAUD+1)
|
|||
|
|
spi1baud = 3;
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case SYSCLK_80M:
|
|||
|
|
spll_div = 2; //pll0 240M
|
|||
|
|
cnt_1us = 7;
|
|||
|
|
spi_baud = 3; //Baud Rate =Fsys clock / (SPI_BAUD+1)
|
|||
|
|
spi1baud = 4;
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case SYSCLK_120M:
|
|||
|
|
spll_div = 1; //pll0 240M
|
|||
|
|
cnt_1us = 10;
|
|||
|
|
spi_baud = 4; //Baud Rate =Fsys clock / (SPI_BAUD+1) //spiclk 120/5 = 24M
|
|||
|
|
spi1baud = 9;
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case SYSCLK_26M:
|
|||
|
|
spll_div = 0;
|
|||
|
|
cnt_1us = 3;
|
|||
|
|
spi_baud = 1;
|
|||
|
|
spi1baud = 1;
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case SYSCLK_13M:
|
|||
|
|
spll_div = 1;
|
|||
|
|
cnt_1us = 1;
|
|||
|
|
spi_baud = 0;
|
|||
|
|
spi1baud = 0;
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case SYSCLK_2M:
|
|||
|
|
spll_div = 1;
|
|||
|
|
cnt_1us = 1;
|
|||
|
|
spi_baud = 0;
|
|||
|
|
spi1baud = 0;
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
default:
|
|||
|
|
return;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
//先判断PLL0是否打开
|
|||
|
|
if(clk_sel <= PLL0DIV_120M) {
|
|||
|
|
if (!(PLL0CON & BIT(12))) {
|
|||
|
|
PLL0CON &= ~(BIT(3) | BIT(4) | BIT(5));
|
|||
|
|
PLL0CON |= BIT(3); //Select PLL/VCO frequency band (PLL大于206M vcos = 0x01, 否则为0)
|
|||
|
|
PLL0CON |= BIT(12); //enable pll0 ldo
|
|||
|
|
delay_us(100); //delay 100us
|
|||
|
|
PLL0DIV = 240 * 65536 / 26; //pll0: 240M, XOSC: 26M
|
|||
|
|
PLL0CON |= BIT(20); //update pll0div to pll0_clk
|
|||
|
|
PLL0CON |= BIT(6); //enable analog pll0
|
|||
|
|
PLL0CON |= BIT(18); //pll0 sdm enable
|
|||
|
|
delay_us(1000); //wait pll0 stable
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
sys.cnt_1us = cnt_1us;
|
|||
|
|
sys.sys_clk = sys_clk;
|
|||
|
|
sys.clk_sel = clk_sel;
|
|||
|
|
uart_baud = (((get_sysclk_nhz() + (sys.uart0baud / 2)) / sys.uart0baud) - 1);
|
|||
|
|
|
|||
|
|
set_sysclk_do(sys_clk, clk_sel,spll_div, spi_baud, spi1baud);
|
|||
|
|
set_peripherals_clkdiv();
|
|||
|
|
update_sd0baud(); //更新下SD0BAUD
|
|||
|
|
update_uart0baud_in_sysclk(uart_baud);
|
|||
|
|
}
|