327 lines
10 KiB
C
327 lines
10 KiB
C
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/**
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******************************************************************************
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* @brief DAC functions of the firmware library.
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "gd32f10x_dac.h"
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#include "gd32f10x_rcc.h"
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/** @addtogroup GD32F10x_Firmware
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* @{
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*/
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/** @defgroup DAC
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* @brief DAC driver modules
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* @{
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*/
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/** @defgroup DAC_Private_Defines
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* @{
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*/
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/* CTLR register bits mask */
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#define CTLR_BITS_CLEAR ((uint32_t)0x00000FFE)
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/* DAC Dual Channels SWTRIG masks */
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#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
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/* DHR registers offsets */
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#define DHR12R1_OFFSET ((uint32_t)0x00000008)
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#define DHR12R2_OFFSET ((uint32_t)0x00000014)
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#define DHR12RD_OFFSET ((uint32_t)0x00000020)
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/* DOR register offset */
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#define DOR_OFFSET ((uint32_t)0x0000002C)
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/**
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* @}
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*/
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/** @defgroup DAC_Private_Functions
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* @{
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*/
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/**
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* @brief Deinitialize the DAC peripheral registers.
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* @param DAC_InitParaStruct: DAC_InitPara structure that contains the
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* configuration information for the selected DAC channel.
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* @retval None
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*/
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void DAC_DeInit(DAC_InitPara *DAC_InitParaStruct)
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{
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/* Enable DAC reset state */
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RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_DACRST, ENABLE);
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/* Release DAC from reset state */
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RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_DACRST, DISABLE);
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/* Initialize the DAC_Trigger */
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DAC_InitParaStruct->DAC_Trigger = DAC_TRIGGER_NONE;
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/* Initialize the DAC_WaveGeneration */
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DAC_InitParaStruct->DAC_WaveType = DAC_WAVEGENE_NONE;
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/* Initialize the DAC_LFSRUnmask_TriangleAmplitude */
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DAC_InitParaStruct->DAC_LFSRNoise_AmplitudeTriangle = DAC_LFSR_BIT0;
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/* Initialize the DAC_OutputBuffer */
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DAC_InitParaStruct->DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
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}
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/**
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* @brief Initialize the DAC peripheral.
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* @param DAC_Channel: the selected DAC channel.
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* This parameter can be one of the following values:
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* @arg DAC_Channel_1: select DAC Channel1
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* @arg DAC_Channel_2: select DAC Channel2
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* @param DAC_InitStruct: DAC_InitTypeDef structure .
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* @retval None
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*/
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void DAC_Init(uint32_t DAC_Channel, DAC_InitPara *DAC_InitParaStruct)
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{
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uint32_t temp1 = 0, temp2 = 0;
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/* DAC CTLR Configuration */
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/* Get the DAC CTLR value */
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temp1 = DAC->CTLR;
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/* Clear BOFF, TEN, TSEL, WAVE and MAMP bits */
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temp1 &= ~(CTLR_BITS_CLEAR << DAC_Channel);
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/* Configure for the DAC channel: buffer output, trigger, wave generation,
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mask/amplitude for wave generation */
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/* Set TSEL and TEN bits according to DAC_Trigger */
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/* Set WAVE bits according to DAC_WaveType */
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/* Set MAMP bits according to DAC_LFSRNoise_AmplitudeTriangle */
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/* Set BOFF bit according to DAC_OutputBuffer */
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temp2 = (DAC_InitParaStruct->DAC_Trigger | DAC_InitParaStruct->DAC_OutputBuffer |
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DAC_InitParaStruct->DAC_WaveType | DAC_InitParaStruct->DAC_LFSRNoise_AmplitudeTriangle);
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/* Calculate CTLR register value */
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temp1 |= temp2 << DAC_Channel;
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/* Write to DAC CTLR */
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DAC->CTLR = temp1;
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}
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/**
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* @brief Enable or disable the DAC channel.
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* @param DAC_Channel: the selected DAC channel.
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* This parameter can be one of the following values:
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* @arg DAC_Channel_1: select DAC Channel1.
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* @arg DAC_Channel_2: select DAC Channel2.
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* @param NewValue: New value of the DAC channel.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void DAC_Enable(uint32_t DAC_Channel, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the selected DAC channel */
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DAC->CTLR |= (DAC_CTLR_DEN1 << DAC_Channel) ;
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} else {
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/* Disable the selected DAC channel */
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DAC->CTLR &= ~(DAC_CTLR_DEN1 << DAC_Channel);
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}
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}
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/**
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* @brief Enable or disable the selected DAC channel software trigger.
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* @param DAC_Channel: the selected DAC channel.
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* This parameter can be one of the following values:
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* @arg DAC_Channel_1: select DAC Channel1
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* @arg DAC_Channel_2: select DAC Channel2
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* @param NewValue: New value of the selected DAC channel software trigger.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void DAC_SoftwareTrigger_Enable(uint32_t DAC_Channel, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable software trigger for DAC channel1 */
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DAC->SWTR |= (uint32_t)DAC_SWTR_SWTR1 << (DAC_Channel >> 4);
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} else {
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/* Disable software trigger for DAC channel1 */
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DAC->SWTR &= ~((uint32_t)DAC_SWTR_SWTR1 << (DAC_Channel >> 4));
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}
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}
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/**
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* @brief Enable or disable simultaneously the two DAC channels software
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* triggers.
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* @param NewValue: new value of the DAC channels software triggers.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void DAC_DualSoftwareTrigger_Enable(TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable software trigger */
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DAC->SWTR |= DUAL_SWTRIG_SET ;
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} else {
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/* Disable software trigger */
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DAC->SWTR &= ~DUAL_SWTRIG_SET;
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}
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}
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/**
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* @brief Enable or disable the selected DAC channel wave generation.
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* @param DAC_Channel: the selected DAC channel.
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* This parameter can be one of the following values:
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* @arg DAC_Channel_1: select DAC Channel1
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* @arg DAC_Channel_2: select DAC Channel2
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* @param DAC_Wave: the wave type to enable or disable.
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* This parameter can be one of the following values:
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* @arg DAC_WAVE_NOISE: noise wave generation
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* @arg DAC_WAVE_TRIANGLE: triangle wave generation
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* @param NewValue: new value of the selected DAC channel wave generation.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void DAC_WaveGeneration_Enable(uint32_t DAC_Channel, uint32_t DAC_Wave, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the selected DAC channel wave generation */
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DAC->CTLR |= DAC_Wave << DAC_Channel;
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} else {
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/* Disable the selected DAC channel wave generation */
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DAC->CTLR &= ~(DAC_Wave << DAC_Channel);
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}
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}
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/**
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* @brief Set the specified data holding register value for DAC channel1.
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* @param DAC_Align: the data alignment for DAC channel1.
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* This parameter can be one of the following values:
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* @arg DAC_ALIGN_8B_R: select 8bit right data alignment
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* @arg DAC_ALIGN_12B_L: select 12bit left data alignment
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* @arg DAC_ALIGN_12B_R: select 12bit right data alignment
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* @param Data: Data to be loaded.
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* @retval None
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*/
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void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
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{
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__IO uint32_t temp = 0;
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temp = (uint32_t)DAC_BASE;
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temp += DHR12R1_OFFSET + DAC_Align;
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/* Set the DAC channel1 */
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*(__IO uint32_t *) temp = Data;
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}
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/**
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* @brief Set the specified data holding register value for DAC channel2.
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* @param DAC_Align: the data alignment for DAC channel2.
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* This parameter can be one of the following values:
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* @arg DAC_ALIGN_8B_R: select 8bit right data alignment
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* @arg DAC_ALIGN_12B_L: select 12bit left data alignment
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* @arg DAC_ALIGN_12B_R: select 12bit right data alignment
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* @param Data: Data to be loaded.
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* @retval None
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*/
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void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
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{
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__IO uint32_t temp = 0;
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temp = (uint32_t)DAC_BASE;
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temp += DHR12R2_OFFSET + DAC_Align;
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/* Set the DAC channel2 */
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*(__IO uint32_t *) temp = Data;
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}
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/**
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* @brief Set the specified data for dual channel
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* @param DAC_Align: the data alignment for dual channel DAC.
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* This parameter can be one of the following values:
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* @arg DAC_Align_8b_R: select 8bit right data alignment
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* @arg DAC_Align_12b_L: select 12bit left data alignment
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* @arg DAC_Align_12b_R: select 12bit right data alignment
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* @param Data2: Data for DAC Channel2.
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* @param Data1: Data for DAC Channel1.
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* @retval None
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*/
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void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
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{
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uint32_t data = 0, temp = 0;
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/* set dual DAC data holding register value */
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if (DAC_Align == DAC_ALIGN_8B_R) {
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data = ((uint32_t)Data2 << 8) | Data1;
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} else {
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data = ((uint32_t)Data2 << 16) | Data1;
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}
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temp = (uint32_t)DAC_BASE;
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temp += DHR12RD_OFFSET + DAC_Align;
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/* Set the dual DAC selected data holding register */
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*(__IO uint32_t *)temp = data;
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}
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/**
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* @brief Return the last data output value.
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* @param DAC_Channel: the selected DAC channel.
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* This parameter can be one of the following values:
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* @arg DAC_Channel_1: select DAC Channel1
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* @arg DAC_Channel_2: select DAC Channel2
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* @retval The DAC channel1 data output value.
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*/
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uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
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{
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__IO uint32_t temp = 0;
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temp = (uint32_t) DAC_BASE;
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temp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
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/* Returns the DAC channel data */
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return (uint16_t)(*(__IO uint32_t *) temp);
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}
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/**
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* @brief Enable or disable DMA request.
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* @param DAC_Channel: the selected DAC channel.
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* This parameter can be one of the following values:
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* @arg DAC_Channel_1: select DAC Channel1
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* @arg DAC_Channel_2: select DAC Channel2
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* @param NewValue: New value of the selected DAC channel DMA request.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void DAC_DMA_Enable(uint32_t DAC_Channel, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable DMA request */
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DAC->CTLR |= (DAC_CTLR_DDMAEN1 << DAC_Channel);
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} else {
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/* Disable DMA request */
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DAC->CTLR &= ~(DAC_CTLR_DDMAEN1 << DAC_Channel);
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}
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}
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/**
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* @brief Enable or disable the specified DAC interrupts.
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* @param DAC_Channel: the selected DAC channel.
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* This parameter can be one of the following values:
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* @arg DAC_Channel_1: DAC Channel1 selected
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* @arg DAC_Channel_2: DAC Channel2 selected
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* @param NewValue: Alternative state of the specified DAC interrupts.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void DAC_INTConfig(uint32_t DAC_Channel, TypeState NewValue)
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{
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if (NewValue != DISABLE) {
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/* Enable the DAC DMAUDR interrupts */
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DAC->CTLR |= (DAC_INT_DMAUDR << DAC_Channel);
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} else {
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/* Disable the DAC DMAUDR interrupts */
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DAC->CTLR &= (~(uint32_t)(DAC_INT_DMAUDR << DAC_Channel));
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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