257 lines
6.9 KiB
C
257 lines
6.9 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-08 shelton first version
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*/
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#include "board.h"
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#ifdef BSP_USING_SDRAM
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#include "drv_sdram.h"
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#define DRV_DEBUG
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#define LOG_TAG "drv.sdram"
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#include <drv_log.h>
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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static struct rt_memheap system_heap;
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#endif
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static void sdram_init_sequence(xmc_cmd_bank1_2_type cmd_bank)
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{
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xmc_sdram_cmd_type sdram_cmd_struct;
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uint32_t timeout = 0xffff, delay = 0;
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sdram_cmd_struct.cmd = XMC_CMD_CLK;
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sdram_cmd_struct.auto_refresh = 1;
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sdram_cmd_struct.cmd_banks = cmd_bank;
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sdram_cmd_struct.data = 0;
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xmc_sdram_cmd(&sdram_cmd_struct);
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while((xmc_flag_status_get(XMC_BANK5_6_SDRAM, XMC_BUSY_FLAG) != RESET) && (timeout > 0))
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{
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timeout --;
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}
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/* insert 100 ms delay */
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for (delay = 0; delay < 0xffff; delay ++)
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;
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sdram_cmd_struct.cmd = XMC_CMD_PRECHARG_ALL;
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sdram_cmd_struct.auto_refresh = 1;
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sdram_cmd_struct.cmd_banks = cmd_bank;
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sdram_cmd_struct.data = 0;
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xmc_sdram_cmd(&sdram_cmd_struct);
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timeout = 0xffff;
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while((xmc_flag_status_get(XMC_BANK5_6_SDRAM, XMC_BUSY_FLAG) != RESET) && (timeout > 0))
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{
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timeout --;
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}
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/* set refresh rate */
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xmc_sdram_refresh_counter_set(SDRAM_REFRESH_COUNT);
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sdram_cmd_struct.cmd = XMC_CMD_AUTO_REFRESH;
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sdram_cmd_struct.auto_refresh = 8;
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sdram_cmd_struct.cmd_banks = cmd_bank;
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sdram_cmd_struct.data = 0;
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xmc_sdram_cmd(&sdram_cmd_struct);
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timeout = 0xffff;
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while((xmc_flag_status_get(XMC_BANK5_6_SDRAM, XMC_BUSY_FLAG) != RESET) && (timeout > 0))
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{
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timeout --;
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}
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sdram_cmd_struct.cmd = XMC_CMD_LOAD_MODE;
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sdram_cmd_struct.auto_refresh = 1;
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sdram_cmd_struct.cmd_banks = cmd_bank;
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#if SDRAM_DATA_WIDTH == 8
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sdram_cmd_struct.data = (uint32_t)SDRAM_BURST_LEN_1 |
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#elif SDRAM_DATA_WIDTH == 16
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sdram_cmd_struct.data = (uint32_t)SDRAM_BURST_LEN_2 |
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#endif
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SDRAM_BURST_SEQUENTIAL |
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#if SDRAM_CAS_LATENCY == 3
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SDRAM_CAS_LATENCY_3 |
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#else
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SDRAM_CAS_LATENCY_2 |
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#endif
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SDRAM_OPERATING_MODE_STANDARD |
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SDRAM_WR_BURST_SINGLE;
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xmc_sdram_cmd(&sdram_cmd_struct);
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timeout = 0xffff;
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while((xmc_flag_status_get(XMC_BANK5_6_SDRAM, XMC_BUSY_FLAG) != RESET) && (timeout > 0))
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{
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timeout --;
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}
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}
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static int sdram_init(void)
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{
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int result = RT_EOK;
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xmc_cmd_bank1_2_type target_bank = XMC_CMD_BANK1;
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xmc_sdram_init_type sdram_init_struct;
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xmc_sdram_timing_type sdram_timing_struct;
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at32_msp_sdram_init(NULL);
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/* xmc configuration */
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xmc_sdram_default_para_init(&sdram_init_struct, &sdram_timing_struct);
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#if SDRAM_TARGET_BANK == 1
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sdram_init_struct.sdram_bank = XMC_SDRAM_BANK1;
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#else
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sdram_init_struct.sdram_bank = XMC_SDRAM_BANK2;
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#endif
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#if SDRAM_COLUMN_BITS == 8
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sdram_init_struct.column_address = XMC_COLUMN_8;
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#elif SDRAM_COLUMN_BITS == 9
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sdram_init_struct.column_address = XMC_COLUMN_9;
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#elif SDRAM_COLUMN_BITS == 10
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sdram_init_struct.column_address = XMC_COLUMN_10;
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#else
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sdram_init_struct.column_address = XMC_COLUMN_11;
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#endif
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#if SDRAM_ROW_BITS == 11
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sdram_init_struct.row_address = XMC_ROW_11;
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#elif SDRAM_ROW_BITS == 12
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sdram_init_struct.row_address = XMC_ROW_12;
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#else
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sdram_init_struct.row_address = XMC_ROW_13;
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#endif
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#if SDRAM_DATA_WIDTH == 8
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sdram_init_struct.width = XMC_MEM_WIDTH_8;
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#elif SDRAM_DATA_WIDTH == 16
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sdram_init_struct.width = XMC_MEM_WIDTH_16;
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#endif
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sdram_init_struct.internel_banks = XMC_INBK_4;
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#if SDRAM_CAS_LATENCY == 1
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sdram_init_struct.cas = XMC_CAS_1;
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#elif SDRAM_CAS_LATENCY == 2
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sdram_init_struct.cas = XMC_CAS_2;
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#else
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sdram_init_struct.cas = XMC_CAS_3;
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#endif
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#if SDRAM_RPIPE_DELAY == 0
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sdram_init_struct.read_delay = XMC_READ_DELAY_0;
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#elif SDRAM_RPIPE_DELAY == 1
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sdram_init_struct.read_delay = XMC_READ_DELAY_1;
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#else
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sdram_init_struct.read_delay = XMC_READ_DELAY_2;
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#endif
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#if SDCLOCK_PERIOD == 2
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sdram_init_struct.clkdiv = XMC_CLKDIV_2;
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#else
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sdram_init_struct.clkdiv = XMC_CLKDIV_3;
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#endif
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sdram_init_struct.write_protection = FALSE;
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sdram_init_struct.burst_read = TRUE;
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sdram_timing_struct.tmrd = LOADTOACTIVEDELAY;
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sdram_timing_struct.txsr = EXITSELFREFRESHDELAY;
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sdram_timing_struct.tras = SELFREFRESHTIME;
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sdram_timing_struct.trc = ROWCYCLEDELAY;
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sdram_timing_struct.twr = WRITERECOVERYTIME;
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sdram_timing_struct.trp = RPDELAY;
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sdram_timing_struct.trcd = RCDDELAY;
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xmc_sdram_init(&sdram_init_struct, &sdram_timing_struct);
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#if SDRAM_TARGET_BANK == 1
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target_bank = XMC_CMD_BANK1;
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#else
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target_bank = XMC_CMD_BANK2;
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#endif
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sdram_init_sequence(target_bank);
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
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rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, SDRAM_SIZE);
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#endif
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return result;
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}
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INIT_BOARD_EXPORT(sdram_init);
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#ifdef DRV_DEBUG
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#ifdef FINSH_USING_MSH
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int sdram_sample(void)
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{
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int i = 0;
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uint32_t start_time = 0, time_cast = 0;
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#if SDRAM_DATA_WIDTH == 8
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char data_width = 1;
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uint8_t data = 0;
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#elif SDRAM_DATA_WIDTH == 16
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char data_width = 2;
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uint16_t data = 0;
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#else
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char data_width = 4;
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uint32_t data = 0;
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#endif
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/* write data */
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LOG_D("writing the %ld bytes data, waiting....", SDRAM_SIZE);
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start_time = rt_tick_get();
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH == 8
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*(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)(i % 100);
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#elif SDRAM_DATA_WIDTH == 16
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*(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)(i % 1000);
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#endif
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}
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time_cast = rt_tick_get() - start_time;
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LOG_D("write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
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time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
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/* read data */
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LOG_D("start reading and verifying data, waiting....");
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for (i = 0; i < SDRAM_SIZE / data_width; i++)
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{
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#if SDRAM_DATA_WIDTH == 8
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data = *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != i % 100)
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{
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LOG_E("sdram test failed!");
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break;
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}
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#elif SDRAM_DATA_WIDTH == 16
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data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width);
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if (data != (uint16_t)(i % 1000))
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{
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LOG_E("sdram test failed, i = %d!", i);
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break;
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}
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#endif
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}
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if (i >= SDRAM_SIZE / data_width)
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{
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LOG_D("sdram test success!");
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}
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return RT_EOK;
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}
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MSH_CMD_EXPORT(sdram_sample, sdram sample test)
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#endif /* FINSH_USING_MSH */
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#endif /* DRV_DEBUG */
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#endif /* BSP_USING_SDRAM */
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