513 lines
12 KiB
C
513 lines
12 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-03-29 shelton first version
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*/
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#include "board.h"
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#include "drv_qspi.h"
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#ifdef BSP_USING_QSPI
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#if !defined(BSP_USING_QSPI1) && !defined(BSP_USING_QSPI2)
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#error "Please define at least one BSP_USING_QSPIx"
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#endif
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#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
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#define QSPI_FIFO_DEPTH (32 * 4)
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#define DRV_DEBUG
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#define LOG_TAG "drv.qspi"
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#include <drv_log.h>
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struct at32_hw_spi_cs
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{
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rt_uint16_t pin;
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};
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struct at32_qspi_bus
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{
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struct rt_spi_bus qspi_device;
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qspi_type *qspi_x;
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char *bus_name;
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};
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enum
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{
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#ifdef BSP_USING_QSPI1
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QSPI1_INDEX,
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#endif
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#ifdef BSP_USING_QSPI2
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QSPI2_INDEX,
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#endif
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};
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static struct at32_qspi_bus at32_qspi_obj[] =
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{
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#ifdef BSP_USING_QSPI1
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QSPI1_BUS_CONFIG,
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#endif
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#ifdef BSP_USING_QSPI2
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QSPI2_BUS_CONFIG,
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#endif
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};
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static int at32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configuration *qspi_cfg)
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{
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int result = RT_EOK;
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unsigned int i = 0;
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crm_clocks_freq_type clocks;
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rt_uint8_t qspi_div_tab[] = {2, 4, 6, 8, 3, 5, 10, 12};
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(qspi_cfg != RT_NULL);
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struct rt_spi_configuration *cfg = &qspi_cfg->parent;
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struct at32_qspi_bus *qspi_bus = device->parent.bus->parent.user_data;
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at32_msp_qspi_init(qspi_bus->qspi_x);
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/* switch to cmd port */
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qspi_xip_enable(qspi_bus->qspi_x, FALSE);
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/* get clocks and config qspi clock div */
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crm_clocks_freq_get(&clocks);
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while (cfg->max_hz < clocks.ahb_freq / qspi_div_tab[i])
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{
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i++;
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if (i == 8)
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{
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LOG_E("qspi init failed, qspi frequency(%d) is too low.", cfg->max_hz);
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return -RT_ERROR;
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}
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}
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/* set qspi sclk */
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qspi_clk_division_set(qspi_bus->qspi_x, (qspi_clk_div_type)i);
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if (!(cfg->mode & RT_SPI_CPOL))
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{
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/* qspi mode0 */
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qspi_sck_mode_set(qspi_bus->qspi_x, QSPI_SCK_MODE_0);
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}
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else
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{
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/* qspi mode3 */
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qspi_sck_mode_set(qspi_bus->qspi_x, QSPI_SCK_MODE_3);
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}
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/* flash size */
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qspi_bus->qspi_x->fsize = POSITION_VAL(qspi_cfg->medium_size) - 1;
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return result;
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}
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static void qspi_send_cmd(struct at32_qspi_bus *qspi_bus, struct rt_qspi_message *message, rt_bool_t dir)
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{
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qspi_cmd_type cmd;
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RT_ASSERT(qspi_bus != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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/* set qspi cmd struct */
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cmd.instruction_code = message->instruction.content;
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cmd.address_code = message->address.content;
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cmd.second_dummy_cycle_num = message->dummy_cycles;
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/* address length */
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if (message->address.size == 0)
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{
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cmd.address_length = QSPI_CMD_ADRLEN_0_BYTE;
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}
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else if (message->address.size == 8)
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{
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cmd.address_length = QSPI_CMD_ADRLEN_1_BYTE;
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}
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else if (message->address.size == 16)
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{
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cmd.address_length = QSPI_CMD_ADRLEN_2_BYTE;
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}
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else if (message->address.size == 24)
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{
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cmd.address_length = QSPI_CMD_ADRLEN_3_BYTE;
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}
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else if (message->address.size == 32)
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{
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cmd.address_length = QSPI_CMD_ADRLEN_4_BYTE;
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}
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/* instruction length */
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if (message->instruction.qspi_lines == 0)
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{
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cmd.instruction_length = QSPI_CMD_INSLEN_0_BYTE;
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}
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else
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{
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cmd.instruction_length = QSPI_CMD_INSLEN_1_BYTE;
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}
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/* operate mode */
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switch(message->instruction.qspi_lines)
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{
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case 0:
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case 1:
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{
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switch(message->address.qspi_lines)
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{
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case 0:
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case 1:
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{
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switch(message->qspi_data_lines)
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{
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case 1:
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{
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cmd.operation_mode = QSPI_OPERATE_MODE_111;
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break;
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}
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case 2:
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{
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cmd.operation_mode = QSPI_OPERATE_MODE_112;
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break;
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}
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case 4:
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{
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cmd.operation_mode = QSPI_OPERATE_MODE_114;
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break;
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}
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default:
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{
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cmd.operation_mode = QSPI_OPERATE_MODE_111;
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break;
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}
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}
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break;
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}
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case 2:
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{
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cmd.operation_mode = QSPI_OPERATE_MODE_122;
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break;
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}
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case 4:
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{
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cmd.operation_mode = QSPI_OPERATE_MODE_144;
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break;
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}
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}
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break;
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}
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case 2:
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{
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cmd.operation_mode = QSPI_OPERATE_MODE_222;
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break;
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}
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case 4:
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{
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cmd.operation_mode = QSPI_OPERATE_MODE_444;
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break;
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}
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default:
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{
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cmd.operation_mode = QSPI_OPERATE_MODE_111;
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break;
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}
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}
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cmd.pe_mode_enable = FALSE;
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cmd.pe_mode_operate_code = 0;
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cmd.read_status_enable = FALSE;
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cmd.read_status_config = QSPI_RSTSC_SW_ONCE;
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if(dir == 1)
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{
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cmd.write_data_enable = TRUE;
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}
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else
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{
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cmd.write_data_enable = FALSE;
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}
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cmd.data_counter = message->parent.length;
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qspi_cmd_operation_kick(qspi_bus->qspi_x, &cmd);
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/* no date need to be processed, wait command completed. */
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if(cmd.data_counter == 0)
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{
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while(qspi_flag_get(qspi_bus->qspi_x, QSPI_CMDSTS_FLAG) == RESET);
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qspi_flag_clear(qspi_bus->qspi_x, QSPI_CMDSTS_FLAG);
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}
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}
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static error_status qspi_data_transmit(struct at32_qspi_bus *qspi_bus, rt_uint8_t* buf, rt_uint32_t length, rt_uint32_t timeout)
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{
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rt_uint32_t index = 0, ticks = 0, len = length;
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for(index = 0; index < len; index++)
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{
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/* wait fifo ready */
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ticks = 0;
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while((qspi_flag_get(qspi_bus->qspi_x, QSPI_TXFIFORDY_FLAG) == RESET) && (ticks <= timeout))
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{
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ticks ++;
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}
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if(ticks >= timeout)
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{
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return ERROR;
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}
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/* write data */
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qspi_byte_write(qspi_bus->qspi_x, *buf++);
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}
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/* wait command completed. */
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ticks = 0;
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while((qspi_flag_get(qspi_bus->qspi_x, QSPI_CMDSTS_FLAG) == RESET) && (ticks <= timeout))
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{
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ticks++;
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}
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if(ticks >= timeout)
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{
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return ERROR;
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}
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/* clear cmdsts flag */
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qspi_flag_clear(qspi_bus->qspi_x, QSPI_CMDSTS_FLAG);
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return SUCCESS;
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}
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static error_status qspi_data_receive(struct at32_qspi_bus *qspi_bus, rt_uint8_t* buf, rt_uint32_t length, rt_uint32_t timeout)
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{
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rt_uint32_t index = 0, ticks = 0, len = 0;
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do
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{
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if(length >= QSPI_FIFO_DEPTH)
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{
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len = QSPI_FIFO_DEPTH;
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}
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else
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{
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len = length;
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}
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/* wait fifo ready */
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ticks = 0;
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while((qspi_flag_get(qspi_bus->qspi_x, QSPI_RXFIFORDY_FLAG) == RESET) && (ticks <= timeout))
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{
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ticks ++;
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}
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if(ticks >= timeout)
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{
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return ERROR;
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}
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/* read data */
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for(index = 0; index < len; index++)
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{
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*buf++ = qspi_byte_read(qspi_bus->qspi_x);
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}
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length -= len;
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} while(length);
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/* wait command completed. */
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ticks = 0;
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while((qspi_flag_get(qspi_bus->qspi_x, QSPI_CMDSTS_FLAG) == RESET) && (ticks <= timeout))
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{
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ticks++;
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}
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if(ticks >= timeout)
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{
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return ERROR;
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}
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/* clear cmdsts flag */
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qspi_flag_clear(qspi_bus->qspi_x, QSPI_CMDSTS_FLAG);
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return SUCCESS;
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}
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static rt_uint32_t qspi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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rt_size_t len = 0;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
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struct at32_qspi_bus *qspi_bus = device->bus->parent.user_data;
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#ifdef BSP_QSPI_USING_SOFTCS
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struct at32_hw_spi_cs *cs = device->parent.user_data;
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#endif
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const rt_uint8_t *sndb = message->send_buf;
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rt_uint8_t *rcvb = message->recv_buf;
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rt_int32_t length = message->length;
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#ifdef BSP_QSPI_USING_SOFTCS
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if (message->cs_take)
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{
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rt_pin_write(cs->pin, 0);
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}
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#endif
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/* send data */
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if (sndb)
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{
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/* dir == 1, send */
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qspi_send_cmd(qspi_bus, qspi_message, 1);
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if (qspi_message->parent.length != 0)
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{
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if(qspi_data_transmit(qspi_bus, (rt_uint8_t *)sndb, length, 0xFFFF) == SUCCESS)
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{
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len = length;
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}
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else
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{
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LOG_E("qspi send data failed!");
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goto __exit;
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}
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}
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else
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{
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len = 1;
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}
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}
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/* recv data */
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else if (rcvb)
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{
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/* dir == 0, recv */
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qspi_send_cmd(qspi_bus, qspi_message, 0);
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if(qspi_data_receive(qspi_bus, (rt_uint8_t *)rcvb, length, 0xFFFF) == SUCCESS)
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{
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len = length;
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}
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else
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{
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LOG_E("qspi recv data failed!");
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goto __exit;
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}
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}
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__exit:
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#ifdef BSP_QSPI_USING_SOFTCS
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||
|
|
if (message->cs_release)
|
||
|
|
{
|
||
|
|
rt_pin_write(cs->pin, 1);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
return len;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
|
||
|
|
{
|
||
|
|
RT_ASSERT(device != RT_NULL);
|
||
|
|
RT_ASSERT(configuration != RT_NULL);
|
||
|
|
|
||
|
|
struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)device;
|
||
|
|
return at32_qspi_init(qspi_device, &qspi_device->config);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_spi_ops at32_qspi_ops =
|
||
|
|
{
|
||
|
|
.configure = qspi_configure,
|
||
|
|
.xfer = qspi_xfer,
|
||
|
|
};
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief this function attach device to qspi bus.
|
||
|
|
* @param device_name qspi device name
|
||
|
|
* @param pin qspi cs pin number
|
||
|
|
* @param data_line_width qspi data lines width, such as 1, 2, 4
|
||
|
|
* @param enter_qspi_mode callback function that lets flash enter qspi mode
|
||
|
|
* @param exit_qspi_mode callback function that lets flash exit qspi mode
|
||
|
|
* @retval 0 : success
|
||
|
|
* -1 : failed
|
||
|
|
*/
|
||
|
|
rt_err_t at32_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
|
||
|
|
{
|
||
|
|
struct rt_qspi_device *qspi_device = RT_NULL;
|
||
|
|
struct at32_hw_spi_cs *cs_pin = RT_NULL;
|
||
|
|
rt_err_t result = RT_EOK;
|
||
|
|
|
||
|
|
RT_ASSERT(bus_name != RT_NULL);
|
||
|
|
RT_ASSERT(device_name != RT_NULL);
|
||
|
|
RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
|
||
|
|
|
||
|
|
qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
|
||
|
|
if (qspi_device == RT_NULL)
|
||
|
|
{
|
||
|
|
LOG_E("no memory, qspi bus attach device failed!");
|
||
|
|
result = RT_ENOMEM;
|
||
|
|
goto __exit;
|
||
|
|
}
|
||
|
|
cs_pin = (struct at32_hw_spi_cs *)rt_malloc(sizeof(struct at32_hw_spi_cs));
|
||
|
|
if (qspi_device == RT_NULL)
|
||
|
|
{
|
||
|
|
LOG_E("no memory, qspi bus attach device failed!");
|
||
|
|
result = RT_ENOMEM;
|
||
|
|
goto __exit;
|
||
|
|
}
|
||
|
|
|
||
|
|
qspi_device->enter_qspi_mode = enter_qspi_mode;
|
||
|
|
qspi_device->exit_qspi_mode = exit_qspi_mode;
|
||
|
|
qspi_device->config.qspi_dl_width = data_line_width;
|
||
|
|
|
||
|
|
cs_pin->pin = pin;
|
||
|
|
#ifdef BSP_QSPI_USING_SOFTCS
|
||
|
|
rt_pin_mode(pin, PIN_MODE_OUTPUT);
|
||
|
|
rt_pin_write(pin, 1);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, (void *)cs_pin);
|
||
|
|
|
||
|
|
__exit:
|
||
|
|
if (result != RT_EOK)
|
||
|
|
{
|
||
|
|
if (qspi_device)
|
||
|
|
{
|
||
|
|
rt_free(qspi_device);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (cs_pin)
|
||
|
|
{
|
||
|
|
rt_free(cs_pin);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int rt_hw_qspi_bus_init(void)
|
||
|
|
{
|
||
|
|
int i = 0;
|
||
|
|
int result = RT_EOK;
|
||
|
|
|
||
|
|
for(i = 0; i < sizeof(at32_qspi_obj) / sizeof(at32_qspi_obj[0]); i++)
|
||
|
|
{
|
||
|
|
at32_qspi_obj[i].qspi_device.parent.user_data = &at32_qspi_obj[i];
|
||
|
|
|
||
|
|
if(rt_qspi_bus_register(&at32_qspi_obj[i].qspi_device, at32_qspi_obj[i].bus_name, &at32_qspi_ops) == RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_D("%s register success", at32_qspi_obj[i].bus_name);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_D("%s register failed", at32_qspi_obj[i].bus_name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
INIT_BOARD_EXPORT(rt_hw_qspi_bus_init);
|
||
|
|
|
||
|
|
#endif /* BSP_USING_QSPI */
|