62 lines
2.1 KiB
C
62 lines
2.1 KiB
C
|
/*
|
||
|
|
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||
|
|
*
|
||
|
|
* SPDX-License-Identifier: Apache-2.0
|
||
|
|
*
|
||
|
|
* Change Logs:
|
||
|
|
* Date Author Notes
|
||
|
|
* 2018-11-06 SummerGift first version
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include "board.h"
|
||
|
|
|
||
|
|
void SystemClock_Config(void)
|
||
|
|
{
|
||
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||
|
|
|
||
|
|
/* Enable voltage range 1 for frequency above 100 Mhz */
|
||
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||
|
|
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||
|
|
|
||
|
|
/* Switch to SMPS regulator instead of LDO */
|
||
|
|
HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY);
|
||
|
|
|
||
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
||
|
|
|
||
|
|
/* MSI Oscillator enabled at reset (4Mhz), activate PLL with MSI as source */
|
||
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4;
|
||
|
|
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||
|
|
RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
|
||
|
|
RCC_OscInitStruct.PLL.PLLM = 1;
|
||
|
|
RCC_OscInitStruct.PLL.PLLN = 80;
|
||
|
|
RCC_OscInitStruct.PLL.PLLR = 2;
|
||
|
|
RCC_OscInitStruct.PLL.PLLP = 2;
|
||
|
|
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||
|
|
RCC_OscInitStruct.PLL.PLLFRACN= 0;
|
||
|
|
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_0;
|
||
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||
|
|
{
|
||
|
|
/* Initialization Error */
|
||
|
|
while(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Select PLL as system clock source and configure bus clocks dividers */
|
||
|
|
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | \
|
||
|
|
RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3);
|
||
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||
|
|
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
|
||
|
|
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||
|
|
{
|
||
|
|
/* Initialization Error */
|
||
|
|
while(1);
|
||
|
|
}
|
||
|
|
}
|