578 lines
16 KiB
C
578 lines
16 KiB
C
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-19 SummerGift first version
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* 2018-12-25 zylx fix some bugs
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* 2019-06-10 SummerGift optimize PHY state detection process
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* 2019-09-03 xiaofan optimize link change detection process
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* 2020-07-17 wanghaijing support h7
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* 2020-11-30 wanghaijing add phy reset
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*/
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#include<rtthread.h>
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#include<rtdevice.h>
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#include "board.h"
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#include "drv_config.h"
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#ifdef BSP_USING_ETH_ARTPI
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#include <netif/ethernetif.h>
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#include "lwipopts.h"
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#include "drv_eth.h"
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/*
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* Emac driver uses CubeMX tool to generate emac and phy's configuration,
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* the configuration files can be found in CubeMX_Config folder.
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*/
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/* debug option */
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#define LOG_TAG "drv.emac"
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#include <drv_log.h>
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#define MAX_ADDR_LEN 6
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struct rt_stm32_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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#ifndef PHY_USING_INTERRUPT_MODE
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rt_timer_t poll_link_timer;
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#endif
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/* interface address info, hw address */
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rt_uint8_t dev_addr[MAX_ADDR_LEN];
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/* ETH_Speed */
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uint32_t ETH_Speed;
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/* ETH_Duplex_Mode */
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uint32_t ETH_Mode;
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};
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static ETH_HandleTypeDef EthHandle;
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static ETH_TxPacketConfig TxConfig;
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static struct rt_stm32_eth stm32_eth_device;
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static uint8_t PHY_ADDR = 0x1F;
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static rt_uint32_t reset_pin = 0;
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#if defined ( __ICCARM__ ) /*!< IAR Compiler */
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#pragma location=0x30040000
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ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
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#pragma location=0x30040060
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ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
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#pragma location=0x30040200
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uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffers */
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#elif defined ( __CC_ARM ) /* MDK ARM Compiler */
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__attribute__((at(0x30040000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
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__attribute__((at(0x30040060))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
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__attribute__((at(0x30040200))) uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffer */
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#elif defined ( __GNUC__ ) /* GNU Compiler */
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ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */
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ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */
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uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE] __attribute__((section(".RxArraySection"))); /* Ethernet Receive Buffers */
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#endif
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#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
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#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
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static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
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{
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unsigned char *buf = (unsigned char *)ptr;
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int i, j;
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for (i = 0; i < buflen; i += 16)
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{
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rt_kprintf("%08X: ", i);
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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rt_kprintf("%02X ", buf[i + j]);
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else
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rt_kprintf(" ");
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rt_kprintf(" ");
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
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rt_kprintf("\n");
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}
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}
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#endif
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static void phy_reset(void)
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{
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rt_pin_write(reset_pin, PIN_LOW);
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rt_thread_mdelay(50);
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rt_pin_write(reset_pin, PIN_HIGH);
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}
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/* EMAC initialization function */
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static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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{
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ETH_MACConfigTypeDef MACConf;
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uint32_t regvalue = 0;
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uint8_t status = RT_EOK;
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__HAL_RCC_D2SRAM3_CLK_ENABLE();
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phy_reset();
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/* ETHERNET Configuration */
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EthHandle.Instance = ETH;
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EthHandle.Init.MACAddr = (rt_uint8_t *)&stm32_eth_device.dev_addr[0];
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EthHandle.Init.MediaInterface = HAL_ETH_RMII_MODE;
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EthHandle.Init.TxDesc = DMATxDscrTab;
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EthHandle.Init.RxDesc = DMARxDscrTab;
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EthHandle.Init.RxBuffLen = ETH_MAX_PACKET_SIZE;
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SCB_InvalidateDCache();
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HAL_ETH_DeInit(&EthHandle);
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/* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
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if (HAL_ETH_Init(&EthHandle) != HAL_OK)
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{
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LOG_E("eth hardware init failed");
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}
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else
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{
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LOG_D("eth hardware init success");
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}
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rt_memset(&TxConfig, 0, sizeof(ETH_TxPacketConfig));
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TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
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TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
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TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
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for (int idx = 0; idx < ETH_RX_DESC_CNT; idx++)
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{
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HAL_ETH_DescAssignMemory(&EthHandle, idx, &Rx_Buff[idx][0], NULL);
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}
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HAL_ETH_SetMDIOClockRange(&EthHandle);
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for(int i = 0; i <= PHY_ADDR; i ++)
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{
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if(HAL_ETH_ReadPHYRegister(&EthHandle, i, PHY_SPECIAL_MODES_REG, ®value) != HAL_OK)
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{
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status = RT_ERROR;
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/* Can't read from this device address continue with next address */
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continue;
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}
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if((regvalue & PHY_BASIC_STATUS_REG) == i)
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{
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PHY_ADDR = i;
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status = RT_EOK;
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LOG_D("Found a phy, address:0x%02X", PHY_ADDR);
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break;
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}
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}
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if(HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK) == HAL_OK)
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{
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_SPECIAL_MODES_REG, ®value);
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uint32_t tickstart = rt_tick_get();
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/* wait until software reset is done or timeout occured */
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while(regvalue & PHY_RESET_MASK)
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{
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if((rt_tick_get() - tickstart) <= 500)
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{
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if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value) != HAL_OK)
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{
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status = RT_ERROR;
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break;
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}
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}
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else
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{
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status = RT_ETIMEOUT;
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}
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}
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}
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rt_thread_delay(2000);
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if(HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, ®value) == HAL_OK)
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{
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regvalue |= PHY_AUTO_NEGOTIATION_MASK;
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HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_CONTROL_REG, regvalue);
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eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
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HAL_ETH_GetMACConfig(&EthHandle, &MACConf);
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MACConf.DuplexMode = ETH_FULLDUPLEX_MODE;
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MACConf.Speed = ETH_SPEED_100M;
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HAL_ETH_SetMACConfig(&EthHandle, &MACConf);
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HAL_ETH_Start_IT(&EthHandle);
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}
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else
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{
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status = RT_ERROR;
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}
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return status;
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}
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static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
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{
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LOG_D("emac open");
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return RT_EOK;
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}
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static rt_err_t rt_stm32_eth_close(rt_device_t dev)
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{
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LOG_D("emac close");
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return RT_EOK;
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}
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static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
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{
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LOG_D("emac read");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
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{
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LOG_D("emac write");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
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{
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switch (cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
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else return -RT_ERROR;
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/* ethernet device interface */
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/* transmit data*/
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rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
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{
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rt_err_t ret = RT_ERROR;
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HAL_StatusTypeDef state;
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uint32_t i = 0, framelen = 0;
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struct pbuf *q;
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ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT];
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rt_memset(Txbuffer, 0, ETH_TX_DESC_CNT * sizeof(ETH_BufferTypeDef));
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for (q = p; q != NULL; q = q->next)
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{
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if (i >= ETH_TX_DESC_CNT)
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return ERR_IF;
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Txbuffer[i].buffer = q->payload;
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Txbuffer[i].len = q->len;
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framelen += q->len;
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if (i > 0)
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{
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Txbuffer[i - 1].next = &Txbuffer[i];
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}
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if (q->next == NULL)
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{
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Txbuffer[i].next = NULL;
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}
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i++;
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}
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TxConfig.Length = framelen;
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TxConfig.TxBuffer = Txbuffer;
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#ifdef ETH_TX_DUMP
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rt_kprintf("Tx dump, len= %d\r\n", framelen);
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dump_hex(&Txbuffer[0]);
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#endif
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if (stm32_eth_device.parent.link_status)
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{
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SCB_CleanInvalidateDCache();
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state = HAL_ETH_Transmit(&EthHandle, &TxConfig, 1000);
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if (state != HAL_OK)
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{
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LOG_W("eth transmit frame faild: %d", EthHandle.ErrorCode);
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EthHandle.ErrorCode = HAL_ETH_STATE_READY;
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EthHandle.gState = HAL_ETH_STATE_READY;
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}
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}
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else
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{
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LOG_E("eth transmit frame faild, netif not up");
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}
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ret = ERR_OK;
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return ret;
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}
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/* receive data*/
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struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
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{
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uint32_t framelength = 0;
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rt_uint16_t l;
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struct pbuf *p = RT_NULL, *q;
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ETH_BufferTypeDef RxBuff;
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uint32_t alignedAddr;
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if(HAL_ETH_GetRxDataBuffer(&EthHandle, &RxBuff) == HAL_OK)
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{
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HAL_ETH_GetRxDataLength(&EthHandle, &framelength);
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/* Build Rx descriptor to be ready for next data reception */
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HAL_ETH_BuildRxDescriptors(&EthHandle);
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/* Invalidate data cache for ETH Rx Buffers */
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alignedAddr = (uint32_t)RxBuff.buffer & ~0x1F;
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SCB_InvalidateDCache_by_Addr((uint32_t *)alignedAddr, (uint32_t)RxBuff.buffer - alignedAddr + framelength);
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p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM);
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if (p != NULL)
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{
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for (q = p, l = 0; q != NULL; q = q->next)
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{
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memcpy((rt_uint8_t *)q->payload, (rt_uint8_t *)&RxBuff.buffer[l], q->len);
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l = l + q->len;
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}
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}
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}
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return p;
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}
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/* interrupt service routine */
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void ETH_IRQHandler(void)
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{
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/* enter interrupt */
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||
|
|
rt_interrupt_enter();
|
||
|
|
|
||
|
|
HAL_ETH_IRQHandler(&EthHandle);
|
||
|
|
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
|
||
|
|
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
|
||
|
|
{
|
||
|
|
rt_err_t result;
|
||
|
|
result = eth_device_ready(&(stm32_eth_device.parent));
|
||
|
|
|
||
|
|
if (result != RT_EOK)
|
||
|
|
LOG_I("RxCpltCallback err = %d", result);
|
||
|
|
}
|
||
|
|
|
||
|
|
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
|
||
|
|
{
|
||
|
|
LOG_E("eth err");
|
||
|
|
}
|
||
|
|
|
||
|
|
enum
|
||
|
|
{
|
||
|
|
PHY_LINK = (1 << 0),
|
||
|
|
PHY_100M = (1 << 1),
|
||
|
|
PHY_FULL_DUPLEX = (1 << 2),
|
||
|
|
};
|
||
|
|
|
||
|
|
static void phy_linkchange()
|
||
|
|
{
|
||
|
|
static rt_uint8_t phy_speed = 0;
|
||
|
|
rt_uint8_t phy_speed_new = 0;
|
||
|
|
rt_uint32_t status;
|
||
|
|
|
||
|
|
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
|
||
|
|
LOG_D("phy basic status reg is 0x%X", status);
|
||
|
|
|
||
|
|
if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
|
||
|
|
{
|
||
|
|
rt_uint32_t SR = 0;
|
||
|
|
|
||
|
|
phy_speed_new |= PHY_LINK;
|
||
|
|
|
||
|
|
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_Status_REG, (uint32_t *)&SR);
|
||
|
|
LOG_D("phy control status reg is 0x%X", SR);
|
||
|
|
|
||
|
|
if (PHY_Status_SPEED_100M(SR))
|
||
|
|
{
|
||
|
|
phy_speed_new |= PHY_100M;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (PHY_Status_FULL_DUPLEX(SR))
|
||
|
|
{
|
||
|
|
phy_speed_new |= PHY_FULL_DUPLEX;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (phy_speed != phy_speed_new)
|
||
|
|
{
|
||
|
|
phy_speed = phy_speed_new;
|
||
|
|
|
||
|
|
if (phy_speed & PHY_LINK)
|
||
|
|
{
|
||
|
|
LOG_D("link up");
|
||
|
|
|
||
|
|
if (phy_speed & PHY_100M)
|
||
|
|
{
|
||
|
|
LOG_D("100Mbps");
|
||
|
|
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
stm32_eth_device.ETH_Speed = ETH_SPEED_10M;
|
||
|
|
LOG_D("10Mbps");
|
||
|
|
}
|
||
|
|
|
||
|
|
if (phy_speed & PHY_FULL_DUPLEX)
|
||
|
|
{
|
||
|
|
LOG_D("full-duplex");
|
||
|
|
stm32_eth_device.ETH_Mode = ETH_FULLDUPLEX_MODE;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_D("half-duplex");
|
||
|
|
stm32_eth_device.ETH_Mode = ETH_HALFDUPLEX_MODE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* send link up. */
|
||
|
|
eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_I("link down");
|
||
|
|
eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef PHY_USING_INTERRUPT_MODE
|
||
|
|
static void eth_phy_isr(void *args)
|
||
|
|
{
|
||
|
|
rt_uint32_t status = 0;
|
||
|
|
|
||
|
|
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
|
||
|
|
LOG_D("phy interrupt status reg is 0x%X", status);
|
||
|
|
|
||
|
|
phy_linkchange();
|
||
|
|
}
|
||
|
|
#endif /* PHY_USING_INTERRUPT_MODE */
|
||
|
|
|
||
|
|
static void phy_monitor_thread_entry(void *parameter)
|
||
|
|
{
|
||
|
|
phy_linkchange();
|
||
|
|
#ifdef PHY_USING_INTERRUPT_MODE
|
||
|
|
/* configuration intterrupt pin */
|
||
|
|
rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
|
||
|
|
rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
|
||
|
|
rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
|
||
|
|
|
||
|
|
/* enable phy interrupt */
|
||
|
|
HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK);
|
||
|
|
#if defined(PHY_INTERRUPT_CTRL_REG)
|
||
|
|
HAL_ETH_WritePHYRegister(&EthHandle, PHY_ADDR, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN);
|
||
|
|
#endif
|
||
|
|
#else /* PHY_USING_INTERRUPT_MODE */
|
||
|
|
stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
|
||
|
|
NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
|
||
|
|
|
||
|
|
if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_E("Start link change detection timer failed");
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* PHY_USING_INTERRUPT_MODE */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Register the EMAC device */
|
||
|
|
static int rt_hw_stm32_eth_init(void)
|
||
|
|
{
|
||
|
|
rt_err_t state = RT_EOK;
|
||
|
|
reset_pin = rt_pin_get(ETH_RESET_PIN);
|
||
|
|
|
||
|
|
rt_pin_mode(reset_pin, PIN_MODE_OUTPUT);
|
||
|
|
rt_pin_write(reset_pin, PIN_HIGH);
|
||
|
|
|
||
|
|
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
||
|
|
stm32_eth_device.ETH_Mode = ETH_FULLDUPLEX_MODE;
|
||
|
|
|
||
|
|
/* OUI 00-80-E1 STMICROELECTRONICS. */
|
||
|
|
stm32_eth_device.dev_addr[0] = 0x00;
|
||
|
|
stm32_eth_device.dev_addr[1] = 0x80;
|
||
|
|
stm32_eth_device.dev_addr[2] = 0xE1;
|
||
|
|
/* generate MAC addr from 96bit unique ID (only for test). */
|
||
|
|
stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4);
|
||
|
|
stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2);
|
||
|
|
stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0);
|
||
|
|
|
||
|
|
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
|
||
|
|
stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
|
||
|
|
stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
|
||
|
|
stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
|
||
|
|
stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
|
||
|
|
stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
|
||
|
|
stm32_eth_device.parent.parent.user_data = RT_NULL;
|
||
|
|
|
||
|
|
stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
|
||
|
|
stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
|
||
|
|
|
||
|
|
/* register eth device */
|
||
|
|
state = eth_device_init(&(stm32_eth_device.parent), "e0");
|
||
|
|
|
||
|
|
if (RT_EOK == state)
|
||
|
|
{
|
||
|
|
LOG_D("emac device init success");
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_E("emac device init faild: %d", state);
|
||
|
|
state = -RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* start phy monitor */
|
||
|
|
rt_thread_t tid;
|
||
|
|
tid = rt_thread_create("phy",
|
||
|
|
phy_monitor_thread_entry,
|
||
|
|
RT_NULL,
|
||
|
|
1024,
|
||
|
|
RT_THREAD_PRIORITY_MAX - 2,
|
||
|
|
2);
|
||
|
|
|
||
|
|
if (tid != RT_NULL)
|
||
|
|
{
|
||
|
|
rt_thread_startup(tid);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
state = -RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
return state;
|
||
|
|
}
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);
|
||
|
|
|
||
|
|
#endif /* BSP_USING_ETH_ARTPI */
|