rt-thread/bsp/gd32/arm/gd32470z-lckfb/project.uvprojx

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[GD32]add gd32470z-lckfb (#7022) * --复制gd32450z-eval 作为立创梁山派 gd32470z-lckfb的模板进行移植 * -修改模板keil工程的配置,IROM需要注意总共为1024k,分为Code area 和Data area ,IRAM1为 : 512K-64K=448K=458752=0x70000。 -重新用ENV生成编译固件 片上SRAM可分为4块,分别为SRAM0(112KB)、SRAM1(16KB)、SRAM2(64KB)和TCMSRAM(64KB)。SRAM0、SRAM1和SRAM2可以被所有的AHB主机访问,然而,TCMSRAM(紧耦合存储器SRAM)只可被Cortex ® -M4内核的数据总线访问。BKPSRAM(备份SRAM)应用于备份域,即使当VDD供电电源掉电时,该SRAM仍可保持其内容。附加SRAM(ADDSRAM)只在一些特殊的GD32F4xx器件中可用。由于采用AHB互联矩阵,上述SRAM块可以同时被不同的AHB主机访问,例如,即使CPU正在访问SRAM0,USBHS也可以访问SRAM1。 * -修改IAR编译的链接脚本 * --修改Flash和RAM大小 -RAM大小为448k是因为512K-64K=448K,其中后面的64K为TCMSRAM(紧耦合存储器SRAM)只可被Cortex ® -M4内核的数据总线访问,先不要乱分配 * -修改MDK链接脚本 * -修改board.h * -修改MCU型号 * -Finsh控制台和LED1闪灯程序工作正常,串口控制台名称错误,从uart改为uart0 -Scons正常生成工程 * -发现GD32固件库当前没有240Mhz的时钟配置,将固件库升级为GD32F4xx_Firmware_Library_V3.0.3-发布时间为2023-01-04 * -修改bsp/gd32/arm/gd32407v-start/board/SConscript文件 * -修改led1和change logs * -按照提交规范使能 One ELF Section per Function(MDK) 并用scons重新生成工程 * -发现整个GD32的IAR模板工程template.eww 是没有的,所以当前是不支持IAR开发的,需要后面学习一下IAR使用再实现了。 * -使用formatting源码格式化工具跑一边gd32470z-lckfb目录 * -使用formatting源码格式化工具跑一遍[components/net/netdev/src/netdev.c] -三个月前的提交多了几个空格
2023-03-11 12:21:31 +08:00
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
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<Header>### uVision Project, (C) Keil Software</Header>
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<PackURL>http://gd32mcu.com/data/documents/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x070000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x0100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
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<uocXRam>0</uocXRam>
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<RvdsMve>0</RvdsMve>
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<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
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<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
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<Size>0x0</Size>
</Ocm1>
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<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
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</Ocm4>
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<Type>0</Type>
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<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
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<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x70000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x100000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
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<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
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</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
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<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
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<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
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<Undefine></Undefine>
<IncludePath>..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\stdio;..\libraries\GD32F4xx_Firmware_Library\GD32F4xx_standard_peripheral\Include;..\..\..\..\components\finsh;..\..\..\..\libcpu\arm\cortex-m4;..\..\..\..\components\libc\compilers\common\include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\gd32_drivers;board;..\..\..\..\libcpu\arm\common;..\libraries\GD32F4xx_Firmware_Library\CMSIS;applications;..\libraries\GD32F4xx_Firmware_Library\CMSIS\GD\GD32F4xx\Include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\include;.;..\..\..\..\components\libc\posix\ipc</IncludePath>
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