228 lines
9.2 KiB
C
228 lines
9.2 KiB
C
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/**
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******************************************************************************
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* @file ft32f0xx_syscfg.c
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* @author FMD AE
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* @brief This file provides firmware functions to manage the following
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* functionalities of the SYSCFG peripheral:
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* + Remapping the memory mapped at 0x00000000
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* + Remapping the DMA channels
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* + Enabling I2C fast mode plus driving capability for I2C pins
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* + Configuring the EXTI lines connection to the GPIO port
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* + Configuring the CFGR2 features (Connecting some internal signal
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* to the break input of TIM1)
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* @version V1.0.0
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* @data 2021-07-01
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "ft32f0xx_syscfg.h"
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/**
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* @brief Deinitializes the SYSCFG registers to their default reset values.
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* @param None
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* @retval None
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* @note MEM_MODE bits are not affected by APB reset.
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* @note MEM_MODE bits took the value from the user option bytes.
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* @note CFGR2 register is not affected by APB reset.
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* @note CLABBB configuration bits are locked when set.
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* @note To unlock the configuration, perform a system reset.
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*/
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void SYSCFG_DeInit(void)
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{
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/* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
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SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
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/* Set EXTICRx registers to reset value */
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SYSCFG->EXTICR[0] = 0;
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SYSCFG->EXTICR[1] = 0;
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SYSCFG->EXTICR[2] = 0;
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SYSCFG->EXTICR[3] = 0;
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/* Set CFGR2 register to reset value: clear SRAM parity error flag */
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SYSCFG->CFGR2 |= 0;
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}
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/**
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* @brief Configures the memory mapping at address 0x00000000.
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* @param SYSCFG_MemoryRemap: selects the memory remapping.
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* This parameter can be one of the following values:
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* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
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* @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
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* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
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* @retval None
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*/
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void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
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{
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uint32_t tmpctrl = 0;
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/* Check the parameter */
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assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
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/* Get CFGR1 register value */
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tmpctrl = SYSCFG->CFGR1;
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/* Clear MEM_MODE bits */
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tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
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/* Set the new MEM_MODE bits value */
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tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
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/* Set CFGR1 register with the new memory remap configuration */
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SYSCFG->CFGR1 = tmpctrl;
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}
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/**
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* @brief Configure the DMA channels remapping.
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* @param SYSCFG_DMARemap: selects the DMA channels remap.
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* This parameter can be one of the following values:
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* @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
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* @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
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* @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
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* @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
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* @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
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* @param NewState: new state of the DMA channel remapping.
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* This parameter can be: ENABLE or DISABLE.
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* @note When enabled, DMA channel of the selected peripheral is remapped
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* @note When disabled, Default DMA channel is mapped to the selected peripheral
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* @note By default TIM17 DMA requests is mapped to channel 1,
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* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
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* TIM17 DMA requests to channel 2 and use
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* SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
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* TIM17 DMA requests to channel 1 (default mapping)
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* @retval None
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*/
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void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Remap the DMA channel */
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SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
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}
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else
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{
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/* use the default DMA channel mapping */
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SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
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}
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}
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/**
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* @brief Configure the I2C fast mode plus driving capability.
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* @param SYSCFG_I2CFastModePlus: selects the pin.
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* This parameter can be one of the following values:
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* @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
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* @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
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* @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
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* @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
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* @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9
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* @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10
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* @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7
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* @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
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*
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* @param NewState: new state of the DMA channel remapping.
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* This parameter can be: ENABLE or DISABLE.
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* @note ENABLE: Enable fast mode plus driving capability for selected I2C pin
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* @note DISABLE: Disable fast mode plus driving capability for selected I2C pin
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* @note For I2C1, fast mode plus driving capability can be enabled on all selected
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* I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
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* on each one of the following pins PB6, PB7, PB8 and PB9.
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* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
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* can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
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* @note For all I2C2 pins fast mode plus driving capability can be enabled
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* only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
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* @retval None
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*/
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void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable fast mode plus driving capability for selected pin */
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SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
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}
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else
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{
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/* Disable fast mode plus driving capability for selected pin */
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SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
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}
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}
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/** @brief select the modulation envelope source
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* @param SYSCFG_IRDAEnv: select the envelope source.
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* This parameter can be a value
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* @arg SYSCFG_IRDA_ENV_SEL_TIM16
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* @arg SYSCFG_IRDA_ENV_SEL_USART1
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* @arg SYSCFG_IRDA_ENV_SEL_USART2
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* @retval None
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*/
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void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv)
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{
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/* Check the parameters */
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assert_param(IS_SYSCFG_IRDA_ENV(SYSCFG_IRDAEnv));
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SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL);
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SYSCFG->CFGR1 |= (SYSCFG_IRDAEnv);
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}
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/**
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* @brief Selects the GPIO pin used as EXTI Line.
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* @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
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* for EXTI lines where x can be (A, B, C, D, E or F).
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* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
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* @note This parameter can be EXTI_PinSourcex where x can be:
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* (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
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* @retval None
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*/
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void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
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{
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uint32_t tmp = 0x00;
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/* Check the parameters */
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assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
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assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
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tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
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SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
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SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
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}
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/**
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* @brief Connect the selected parameter to the break input of TIM1.
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* @note The selected configuration is locked and can be unlocked by system reset
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* @param SYSCFG_Break: selects the configuration to be connected to break
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* input of TIM1
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* This parameter can be any combination of the following values:
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* @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1
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* @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
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* @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
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* @retval None
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*/
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void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
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{
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/* Check the parameter */
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assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
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SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT FMD *****END OF FILE****/
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