414 lines
14 KiB
C
414 lines
14 KiB
C
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/*
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* @brief LPC5410X Pin Interrupt and Pattern Match Registers and driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __PININT_5410X_H_
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#define __PININT_5410X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup PININT_5410X CHIP: LPC5410X Pin Interrupt and Pattern Match driver
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* @ingroup CHIP_5410X_DRIVERS
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* @{
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*/
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/**
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* @brief LPC5410X Pin Interrupt and Pattern Match register block structure
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*/
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typedef struct { /*!< PIN_INT Structure */
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__IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
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__IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */
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__IO uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */
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__IO uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */
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__IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */
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__IO uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */
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__IO uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */
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__IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */
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__IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */
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__IO uint32_t IST; /*!< Pin Interrupt Status register */
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__IO uint32_t PMCTRL; /*!< GPIO pattern match interrupt control register */
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__IO uint32_t PMSRC; /*!< GPIO pattern match interrupt bit-slice source register */
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__IO uint32_t PMCFG; /*!< GPIO pattern match interrupt bit slice configuration register */
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} LPC_PIN_INT_T;
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/**
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* LPC5410X Pin Interrupt and Pattern match engine register
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* bit fields and macros
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*/
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/* PININT Interrupt Mode Mask */
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#define PININT_ISEL_PMODE_MASK ((uint32_t) 0x00FF)
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/* PININT Pattern Match Control Register Mask */
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#define PININT_PMCTRL_MASK ((uint32_t) 0xFF000003)
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/* PININT interrupt control register */
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#define PININT_PMCTRL_PMATCH_SEL (1 << 0)
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#define PININT_PMCTRL_RXEV_ENA (1 << 1)
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/* PININT Bit slice source register bits */
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#define PININT_SRC_BITSOURCE_START 8
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#define PININT_SRC_BITSOURCE_MASK 7
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/* PININT Bit slice configuration register bits */
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#define PININT_SRC_BITCFG_START 8
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#define PININT_SRC_BITCFG_MASK 7
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/**
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* LPC5410X Pin Interrupt channel values
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*/
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#define PININTCH0 (1 << 0)
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#define PININTCH1 (1 << 1)
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#define PININTCH2 (1 << 2)
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#define PININTCH3 (1 << 3)
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#define PININTCH4 (1 << 4)
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#define PININTCH5 (1 << 5)
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#define PININTCH6 (1 << 6)
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#define PININTCH7 (1 << 7)
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#define PININTCH(ch) (1 << (ch))
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/**
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* LPC5410X Pin Interrupt select enum values
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*/
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typedef enum Chip_PININT_SELECT {
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PININTSELECT0 = 0,
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PININTSELECT1 = 1,
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PININTSELECT2 = 2,
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PININTSELECT3 = 3,
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PININTSELECT4 = 4,
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PININTSELECT5 = 5,
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PININTSELECT6 = 6,
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PININTSELECT7 = 7
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} Chip_PININT_SELECT_T;
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/**
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* LPC5410X Pin Matching Interrupt bit slice enum values
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*/
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typedef enum Chip_PININT_BITSLICE {
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PININTBITSLICE0 = 0, /*!< PININT Bit slice 0 */
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PININTBITSLICE1 = 1, /*!< PININT Bit slice 1 */
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PININTBITSLICE2 = 2, /*!< PININT Bit slice 2 */
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PININTBITSLICE3 = 3, /*!< PININT Bit slice 3 */
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PININTBITSLICE4 = 4, /*!< PININT Bit slice 4 */
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PININTBITSLICE5 = 5, /*!< PININT Bit slice 5 */
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PININTBITSLICE6 = 6, /*!< PININT Bit slice 6 */
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PININTBITSLICE7 = 7 /*!< PININT Bit slice 7 */
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} Chip_PININT_BITSLICE_T;
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/**
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* LPC5410X Pin Matching Interrupt bit slice configuration enum values
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*/
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typedef enum Chip_PININT_BITSLICE_CFG {
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PININT_PATTERNCONST1 = 0x0, /*!< Contributes to product term match */
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PININT_PATTERNRISING = 0x1, /*!< Rising edge */
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PININT_PATTERNFALLING = 0x2, /*!< Falling edge */
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PININT_PATTERNRISINGORFALLING = 0x3, /*!< Rising or Falling edge */
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PININT_PATTERNHIGH = 0x4, /*!< High level */
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PININT_PATTERNLOW = 0x5, /*!< Low level */
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PININT_PATTERNCONST0 = 0x6, /*!< Never contributes for match */
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PININT_PATTERNEVENT = 0x7 /*!< Match occurs on event */
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} Chip_PININT_BITSLICE_CFG_T;
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/**
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* @brief Initialize Pin interrupt block
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* @param pPININT : The base address of Pin interrupt block
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* @return Nothing
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* @note This function should be used after the Chip_GPIO_Init() function.
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*/
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STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT)
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{
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Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_PINT);
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Chip_SYSCON_PeriphReset(RESET_PINT);
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}
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/**
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* @brief De-Initialize Pin interrupt block
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* @param pPININT : The base address of Pin interrupt block
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT)
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{
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Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_PINT);
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}
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/**
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* @brief Configure the pins as edge sensitive in Pin interrupt block
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* @param pPININT : The base address of Pin interrupt block
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* @param pins : Pins (ORed value of PININTCH*)
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_SetPinModeEdge(LPC_PIN_INT_T *pPININT, uint32_t pins)
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{
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pPININT->ISEL = (pPININT->ISEL & PININT_ISEL_PMODE_MASK) & ~pins;
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}
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/**
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* @brief Configure the pins as level sensitive in Pin interrupt block
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* @param pPININT : The base address of Pin interrupt block
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* @param pins : Pins (ORed value of PININTCH*)
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_SetPinModeLevel(LPC_PIN_INT_T *pPININT, uint32_t pins)
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{
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pPININT->ISEL = (pPININT->ISEL & PININT_ISEL_PMODE_MASK) | pins;
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}
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/**
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* @brief Return current PININT edge or level sensitive interrupt selection state
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* @param pPININT : The base address of Pin interrupt block
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* @return A bifield containing the edge/level sensitive selection for each
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* interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
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* For each bit, a 0 means the edge sensitive interrupt is selected, while a 1
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* means the level sensitive interrupt is selected.
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*/
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STATIC INLINE uint32_t Chip_PININT_GetPinMode(LPC_PIN_INT_T *pPININT)
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{
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return pPININT->ISEL & PININT_ISEL_PMODE_MASK;
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}
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/**
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* @brief Return current PININT rising edge or level interrupt enable state
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* @param pPININT : The base address of Pin interrupt block
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* @return A bifield containing the rising edge/level enable for each
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* interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
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* For each bit, a 0 means the rising edge/level interrupt is disabled, while a 1
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* means it's enabled.
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*/
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STATIC INLINE uint32_t Chip_PININT_GetHighEnabled(LPC_PIN_INT_T *pPININT)
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{
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return pPININT->IENR;
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}
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/**
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* @brief Enable rising edge/level PININT interrupts for pins
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* @param pPININT : The base address of Pin interrupt block
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* @param pins : Pins to enable (ORed value of PININTCH*)
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_EnableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
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{
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pPININT->SIENR = pins;
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}
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/**
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* @brief Disable rising edge/level PININT interrupts for pins
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* @param pPININT : The base address of Pin interrupt block
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* @param pins : Pins to disable (ORed value of PININTCH*)
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_DisableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
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{
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pPININT->CIENR = pins;
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}
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/**
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* @brief Return current PININT falling edge or level interrupt active level enable state
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* @param pPININT : The base address of Pin interrupt block
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* @return A bifield containing the falling edge/level interrupt active level enable for each
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* interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
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* For each bit, a 0 means the falling edge is disabled/level interrupt active low is enabled, while a 1
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* means the falling edge is enabled/level interrupt active high is enabled.
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*/
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STATIC INLINE uint32_t Chip_PININT_GetLowEnabled(LPC_PIN_INT_T *pPININT)
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{
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return pPININT->IENF;
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}
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/**
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* @brief Enable falling edge/level active level PININT interrupts for pins
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* @param pPININT : The base address of Pin interrupt block
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* @param pins : Pins to enable (ORed value of PININTCH*)
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_EnableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
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{
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pPININT->SIENF = pins;
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}
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/**
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* @brief Disable low edge/level active level PININT interrupts for pins
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* @param pPININT : The base address of Pin interrupt block
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* @param pins : Pins to disable (ORed value of PININTCH*)
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_DisableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
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{
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pPININT->CIENF = pins;
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}
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/**
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* @brief Return pin states that have a detected latched rising edge (RISE) state
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* @param pPININT : The base address of Pin interrupt block
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* @return PININT states (bit n = high) with a latched rise state detected
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*/
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STATIC INLINE uint32_t Chip_PININT_GetRiseStates(LPC_PIN_INT_T *pPININT)
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{
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return pPININT->RISE;
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}
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/**
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* @brief Clears pin states that had a latched rising edge (RISE) state
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* @param pPININT : The base address of Pin interrupt block
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* @param pins : Pins with latched states to clear
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_ClearRiseStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
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{
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pPININT->RISE = pins;
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}
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/**
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* @brief Return pin states that have a detected latched falling edge (FALL) state
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* @param pPININT : The base address of Pin interrupt block
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* @return PININT states (bit n = high) with a latched rise state detected
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*/
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STATIC INLINE uint32_t Chip_PININT_GetFallStates(LPC_PIN_INT_T *pPININT)
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{
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return pPININT->FALL;
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}
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/**
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* @brief Clears pin states that had a latched falling edge (FALL) state
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* @param pPININT : The base address of Pin interrupt block
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* @param pins : Pins with latched states to clear
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_ClearFallStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
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{
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pPININT->FALL = pins;
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}
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/**
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* @brief Get interrupt status from Pin interrupt block
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* @param pPININT : The base address of Pin interrupt block
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* @return Interrupt status (bit n for PININTn = high means interrupt ie pending)
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*/
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STATIC INLINE uint32_t Chip_PININT_GetIntStatus(LPC_PIN_INT_T *pPININT)
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{
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return pPININT->IST;
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}
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/**
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* @brief Clear interrupt status in Pin interrupt block
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* @param pPININT : The base address of Pin interrupt block
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* @param pins : Pin interrupts to clear (ORed value of PININTCH*)
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* @return Nothing
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*/
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STATIC INLINE void Chip_PININT_ClearIntStatus(LPC_PIN_INT_T *pPININT, uint32_t pins)
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{
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pPININT->IST = pins;
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}
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/**
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* @brief Set source for pattern match in Pin interrupt block
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* @param pPININT : The base address of Pin interrupt block
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* @param channelNum : PININT channel number (From 0 to 7)
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* @param sliceNum : PININT slice number
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* @return Nothing
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*/
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void Chip_PININT_SetPatternMatchSrc(LPC_PIN_INT_T *pPININT,
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Chip_PININT_SELECT_T channelNum,
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Chip_PININT_BITSLICE_T sliceNum);
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/**
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* @brief Configure the pattern matcch in Pin interrupt block
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* @param pPININT : The base address of Pin interrupt block
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* @param sliceNum : PININT slice number
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* @param slice_cfg : PININT slice configuration value (enum Chip_PININT_BITSLICE_CFG_T)
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* @param end_point : If true, current slice is final component
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
|
void Chip_PININT_SetPatternMatchConfig(LPC_PIN_INT_T *pPININT, Chip_PININT_BITSLICE_T sliceNum,
|
||
|
|
Chip_PININT_BITSLICE_CFG_T slice_cfg, bool end_point);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable pattern match interrupts in Pin interrupt block
|
||
|
|
* @param pPININT : The base address of Pin interrupt block
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_PININT_EnablePatternMatch(LPC_PIN_INT_T *pPININT)
|
||
|
|
{
|
||
|
|
pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) | PININT_PMCTRL_PMATCH_SEL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable pattern match interrupts in Pin interrupt block
|
||
|
|
* @param pPININT : The base address of Pin interrupt block
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_PININT_DisablePatternMatch(LPC_PIN_INT_T *pPININT)
|
||
|
|
{
|
||
|
|
pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) & ~PININT_PMCTRL_PMATCH_SEL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enable RXEV output in Pin interrupt block
|
||
|
|
* @param pPININT : The base address of Pin interrupt block
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_PININT_EnablePatternMatchRxEv(LPC_PIN_INT_T *pPININT)
|
||
|
|
{
|
||
|
|
pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) | PININT_PMCTRL_RXEV_ENA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable RXEV output in Pin interrupt block
|
||
|
|
* @param pPININT : The base address of Pin interrupt block
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_PININT_DisablePatternMatchRxEv(LPC_PIN_INT_T *pPININT)
|
||
|
|
{
|
||
|
|
pPININT->PMCTRL = (pPININT->PMCTRL & PININT_PMCTRL_MASK) & ~PININT_PMCTRL_RXEV_ENA;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return pattern match state
|
||
|
|
* @param pPININT : The base address of Pin interrupt block
|
||
|
|
* @return 8 bit pattern match state, where a 1 in any bit indicates that
|
||
|
|
* the corresponding product term has matched by the current state
|
||
|
|
* of its inputs.
|
||
|
|
*/
|
||
|
|
STATIC INLINE uint32_t Chip_PININT_GetPatternMatchState(LPC_PIN_INT_T *pPININT)
|
||
|
|
{
|
||
|
|
return pPININT->PMCTRL >> 24;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __PININT_5410X_H_ */
|