474 lines
14 KiB
C
474 lines
14 KiB
C
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/*
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* @brief LPC5410X clock driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licenser disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CLOCK_5410X_H_
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#define __CLOCK_5410X_H_
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#include "pll_5410x.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CLOCK_5410X CHIP: LPC5410X Clock Driver
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* @ingroup CHIP_5410X_DRIVERS
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* @{
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*/
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/* Internal oscillator frequency */
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#define SYSCON_IRC_FREQ (12000000)
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#define SYSCON_WDTOSC_FREQ (500000)
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#define SYSCON_RTC_FREQ (32768)
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/**
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* @brief Returns the internal oscillator (IRC) clock rate
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* @return internal oscillator (IRC) clock rate
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*/
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STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
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{
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return SYSCON_IRC_FREQ;
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}
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/**
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* @brief Returns the external clock input rate
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* @return External clock input rate
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*/
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STATIC INLINE uint32_t Chip_Clock_GetExtClockInRate(void)
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{
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return ExtClockIn;
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}
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/**
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* @brief Returns the RTC clock rate
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* @return RTC oscillator clock rate in Hz
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*/
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STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
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{
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return SYSCON_RTC_FREQ;
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}
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/**
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* @brief Return estimated watchdog oscillator rate
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* @return Estimated watchdog oscillator rate
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* @note This rate is accurate to plus or minus 40%.
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*/
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STATIC INLINE uint32_t Chip_Clock_GetWDTOSCRate(void)
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{
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return SYSCON_WDTOSC_FREQ;
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}
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/**
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* Clock source selections for only the main A system clock. The main A system
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* clock is used as an input into the main B system clock selector. Main clock A
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* only needs to be setup if the main clock A input is used in the main clock
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* system selector.
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*/
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typedef enum {
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SYSCON_MAIN_A_CLKSRC_IRC = 0, /*!< Internal oscillator */
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SYSCON_MAIN_A_CLKSRCA_CLKIN, /*!< Crystal (main) oscillator in */
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SYSCON_MAIN_A_CLKSRCA_WDTOSC, /*!< Watchdog oscillator rate */
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} CHIP_SYSCON_MAIN_A_CLKSRC_T;
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/**
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* @brief Set main A system clock source
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* @param src : Clock source for main A
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* @return Nothing
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* @note This function only needs to be setup if main clock A will be
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* selected in the Chip_Clock_GetMain_B_ClockRate() function.
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*/
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STATIC INLINE void Chip_Clock_SetMain_A_ClockSource(CHIP_SYSCON_MAIN_A_CLKSRC_T src)
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{
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LPC_SYSCON->MAINCLKSELA = (uint32_t) src;
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}
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/**
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* @brief Returns the main A clock source
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* @return Returns which clock is used for the main A
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*/
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STATIC INLINE CHIP_SYSCON_MAIN_A_CLKSRC_T Chip_Clock_GetMain_A_ClockSource(void)
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{
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return (CHIP_SYSCON_MAIN_A_CLKSRC_T) (LPC_SYSCON->MAINCLKSELA);
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}
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/**
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* @brief Return main A clock rate
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* @return main A clock rate in Hz
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*/
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uint32_t Chip_Clock_GetMain_A_ClockRate(void);
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/**
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* Clock sources for only main B system clock
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*/
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typedef enum {
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SYSCON_MAIN_B_CLKSRC_MAINCLKSELA = 0, /*!< main clock A */
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SYSCON_MAIN_B_CLKSRC_SYSPLLIN, /*!< System PLL input */
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SYSCON_MAIN_B_CLKSRC_SYSPLLOUT, /*!< System PLL output */
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SYSCON_MAIN_B_CLKSRC_RTC, /*!< RTC oscillator 32KHz output */
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} CHIP_SYSCON_MAIN_B_CLKSRC_T;
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/**
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* @brief Set main B system clock source
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* @param src : Clock source for main B
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_SetMain_B_ClockSource(CHIP_SYSCON_MAIN_B_CLKSRC_T src)
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{
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LPC_SYSCON->MAINCLKSELB = (uint32_t) src;
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}
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/**
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* @brief Returns the main B clock source
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* @return Returns which clock is used for the main B
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*/
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STATIC INLINE CHIP_SYSCON_MAIN_B_CLKSRC_T Chip_Clock_GetMain_B_ClockSource(void)
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{
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return (CHIP_SYSCON_MAIN_B_CLKSRC_T) (LPC_SYSCON->MAINCLKSELB);
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}
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/**
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* @brief Return main B clock rate
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* @return main B clock rate
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*/
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uint32_t Chip_Clock_GetMain_B_ClockRate(void);
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/**
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* Clock sources for CLKOUT
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*/
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typedef enum {
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SYSCON_CLKOUTSRC_MAINCLK = 0, /*!< Main system clock for CLKOUT */
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SYSCON_CLKOUTSRC_CLKIN, /*!< CLKIN for CLKOUT */
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SYSCON_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */
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SYSCON_CLKOUTSRC_IRC, /*!< Internal oscillator for CLKOUT */
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SYSCON_CLKOUTSRCA_OUTPUT, /*!< clkoutA output route to input of clkoutB */
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SYSCON_CLKOUTSRC_RTC = 7 /*!< RTC oscillator 32KHz for CLKOUT */
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} CHIP_SYSCON_CLKOUTSRC_T;
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/**
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* @brief Set CLKOUT clock source and divider
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* @param src : Clock source for CLKOUT
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* @param div : divider for CLKOUT clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
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* rate is the clock source divided by the divider. This function will
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* also toggle the clock source update register to update the clock
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* source.
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*/
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void Chip_Clock_SetCLKOUTSource(CHIP_SYSCON_CLKOUTSRC_T src, uint32_t div);
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/**
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* System and peripheral clocks enum
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*/
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typedef enum CHIP_SYSCON_CLOCK {
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/* Peripheral clock enables for SYSAHBCLKCTRL0 */
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SYSCON_CLOCK_ROM = 1, /*!< ROM clock */
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SYSCON_CLOCK_SRAM1 = 3, /*!< SRAM1 clock */
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SYSCON_CLOCK_SRAM2, /*!< SRAM2 clock */
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SYSCON_CLOCK_FLASH = 7, /*!< FLASH controller clock */
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SYSCON_CLOCK_FMC, /*!< FMC clock */
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SYSCON_CLOCK_INPUTMUX = 11, /*!< Input mux clock */
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SYSCON_CLOCK_IOCON = 13, /*!< IOCON clock */
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SYSCON_CLOCK_GPIO0, /*!< GPIO0 clock */
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SYSCON_CLOCK_GPIO1, /*!< GPIO1 clock */
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SYSCON_CLOCK_PINT = 18, /*!< PININT clock */
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SYSCON_CLOCK_GINT, /*!< grouped pin interrupt block clock */
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SYSCON_CLOCK_DMA, /*!< DMA clock */
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SYSCON_CLOCK_CRC, /*!< CRC clock */
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SYSCON_CLOCK_WWDT, /*!< WDT clock */
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SYSCON_CLOCK_RTC, /*!< RTC clock */
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SYSCON_CLOCK_MAILBOX = 26, /*!< Mailbox clock */
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SYSCON_CLOCK_ADC0, /*!< ADC0 clock */
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/* Peripheral clock enables for SYSAHBCLKCTRL1 */
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SYSCON_CLOCK_MRT = 32, /*!< multi-rate timer clock */
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SYSCON_CLOCK_RIT, /*!< Repetitive interval timer clock */
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SYSCON_CLOCK_SCT0, /*!< SCT0 clock */
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SYSCON_CLOCK_FIFO = 32 + 9, /*!< System FIFO clock */
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SYSCON_CLOCK_UTICK, /*!< UTICK clock */
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SYSCON_CLOCK_TIMER2 = 32 + 22, /*!< TIMER2 clock */
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SYSCON_CLOCK_TIMER3 = 32 + 26, /*!< TIMER3 clock */
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SYSCON_CLOCK_TIMER4, /*!< TIMER4 clock */
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/* Peripheral clock enables for ASYNCAPBCLKCTRLCLR */
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SYSCON_CLOCK_USART0 = 128 + 1, /*!< USART0 clock */
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SYSCON_CLOCK_USART1, /*!< USART1 clock */
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SYSCON_CLOCK_USART2, /*!< USART2 clock */
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SYSCON_CLOCK_USART3, /*!< USART3 clock */
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SYSCON_CLOCK_I2C0, /*!< I2C0 clock */
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SYSCON_CLOCK_I2C1, /*!< I2C1 clock */
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SYSCON_CLOCK_I2C2, /*!< I2C2 clock */
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SYSCON_CLOCK_SPI0 = 128 + 9, /*!< SPI0 clock */
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SYSCON_CLOCK_SPI1, /*!< SPI1 clock */
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SYSCON_CLOCK_TIMER0 = 128 + 13, /*!< TIMER0 clock */
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SYSCON_CLOCK_TIMER1, /*!< TIMER1 clock */
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SYSCON_CLOCK_FRG /*!< FRG clock */
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} CHIP_SYSCON_CLOCK_T;
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/**
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* @brief Enable a system or peripheral clock
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* @param clk : Clock to enable
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* @return Nothing
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*/
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void Chip_Clock_EnablePeriphClock(CHIP_SYSCON_CLOCK_T clk);
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/**
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* @brief Disable a system or peripheral clock
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* @param clk : Clock to disable
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* @return Nothing
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*/
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void Chip_Clock_DisablePeriphClock(CHIP_SYSCON_CLOCK_T clk);
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/**
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* @brief Set system tick clock divider (external CLKIN as SYSTICK reference only)
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* @param div : divider for system clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The system tick
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* rate is the external CLKIN rate divided by this value. The extern CLKIN pin
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* signal, divided by the SYSTICKCLKDIV divider, is selected by clearing
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* CLKSOURCE bit 2 in the System Tick CSR register. The core clock must be at least
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* 2.5 times faster than the reference system tick clock otherwise the count
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* values are unpredictable.
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*/
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STATIC INLINE void Chip_Clock_SetSysTickClockDiv(uint32_t div)
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{
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LPC_SYSCON->SYSTICKCLKDIV = div;
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}
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/**
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* @brief Returns system tick clock divider
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* @return system tick clock divider
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*/
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STATIC INLINE uint32_t Chip_Clock_GetSysTickClockDiv(void)
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{
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return LPC_SYSCON->SYSTICKCLKDIV;
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}
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/**
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* @brief Returns the system tick rate as used with the system tick divider
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* @return the system tick rate
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*/
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uint32_t Chip_Clock_GetSysTickClockRate(void);
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/**
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* @brief Set system clock divider
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* @param div : divider for system clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The system clock
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* rate is the main system clock divided by this value.
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*/
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STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
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{
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LPC_SYSCON->AHBCLKDIV = div;
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}
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/**
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* @brief Set system tick clock divider
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* @param div : divider for system clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The system tick
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* rate is the main system clock divided by this value. Use caution when using
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* the CMSIS SysTick_Config() functions as they typically use SystemCoreClock
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* for setup.
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*/
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STATIC INLINE void Chip_Clock_SetADCClockDiv(uint32_t div)
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{
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LPC_SYSCON->ADCCLKDIV = div;
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}
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/**
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* @brief Returns ADC clock divider
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* @return ADC clock divider, 0 = disabled
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*/
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STATIC INLINE uint32_t Chip_Clock_GetADCClockDiv(void)
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{
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return LPC_SYSCON->ADCCLKDIV;
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}
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/**
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* Clock sources for ADC clock source select
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*/
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typedef enum {
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SYSCON_ADCCLKSELSRC_MAINCLK = 0, /*!< Main clock */
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SYSCON_ADCCLKSELSRC_SYSPLLOUT, /*!< PLL output */
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SYSCON_ADCCLKSELSRC_IRC /*!< Internal oscillator */
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} CHIP_SYSCON_ADCCLKSELSRC_T;
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/**
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* @brief Set the ADC clock source
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* @param src : ADC clock source
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_SetADCClockSource(CHIP_SYSCON_ADCCLKSELSRC_T src)
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{
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LPC_SYSCON->ADCCLKSEL = (uint32_t) src;
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}
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/**
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* @brief Returns the ADC clock source
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* @return Returns which clock is used for the ADC clock source
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*/
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STATIC INLINE CHIP_SYSCON_ADCCLKSELSRC_T Chip_Clock_GetADCClockSource(void)
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{
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return (CHIP_SYSCON_ADCCLKSELSRC_T) (LPC_SYSCON->ADCCLKSEL);
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}
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/**
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* @brief Return ADC clock rate
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* @return ADC clock rate
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*/
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uint32_t Chip_Clock_GetADCClockRate(void);
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/**
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* @brief Enable the RTC 32KHz output
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* @return Nothing
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* @note This clock can be used for the main clock directly, but
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* do not use this clock with the system PLL.
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*/
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STATIC INLINE void Chip_Clock_EnableRTCOsc(void)
|
||
|
|
{
|
||
|
|
LPC_SYSCON->RTCOSCCTRL = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disable the RTC 32KHz output
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
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STATIC INLINE void Chip_Clock_DisableRTCOsc(void)
|
||
|
|
{
|
||
|
|
LPC_SYSCON->RTCOSCCTRL = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Clock source selections for the asynchronous APB clock
|
||
|
|
*/
|
||
|
|
typedef enum {
|
||
|
|
SYSCON_ASYNC_IRC = 0, /*!< IRC input */
|
||
|
|
SYSCON_ASYNC_WDTOSC, /*!< Watchdog oscillator */
|
||
|
|
SYSCON_ASYNC_MAINCLK = 4, /*!< Main clock */
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||
|
|
SYSCON_ASYNC_CLKIN, /*!< external CLK input */
|
||
|
|
SYSCON_ASYNC_SYSPLLOUT /*!< System PLL output */
|
||
|
|
} CHIP_ASYNC_SYSCON_SRC_T;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set asynchronous APB clock source
|
||
|
|
* @param src : Clock source for asynchronous APB clock
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
|
void Chip_Clock_SetAsyncSysconClockSource(CHIP_ASYNC_SYSCON_SRC_T src);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get asynchronous APB clock source
|
||
|
|
* @return Clock source for asynchronous APB clock
|
||
|
|
*/
|
||
|
|
CHIP_ASYNC_SYSCON_SRC_T Chip_Clock_GetAsyncSysconClockSource(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return asynchronous APB clock rate
|
||
|
|
* @return Asynchronous APB clock rate
|
||
|
|
* @note Includes adjustments by Async clock divider (ASYNCCLKDIV).
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetAsyncSyscon_ClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set UART divider clock
|
||
|
|
* @param div : divider for UART clock
|
||
|
|
* @return Nothing
|
||
|
|
* @note Use 0 to disable, or a divider value of 1 to 255. The UART clock
|
||
|
|
* rate is the main system clock divided by this value.
|
||
|
|
*/
|
||
|
|
STATIC INLINE void Chip_Clock_SetAsyncSysconClockDiv(uint32_t div)
|
||
|
|
{
|
||
|
|
LPC_ASYNC_SYSCON->ASYNCCLKDIV = div;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Clock sources for main system clock. This is a mix of both main clock A
|
||
|
|
* and B selections.
|
||
|
|
*/
|
||
|
|
typedef enum {
|
||
|
|
SYSCON_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */
|
||
|
|
SYSCON_MAINCLKSRC_CLKIN, /*!< Crystal (main) oscillator in */
|
||
|
|
SYSCON_MAINCLKSRC_WDTOSC, /*!< Watchdog oscillator rate */
|
||
|
|
SYSCON_MAINCLKSRC_PLLIN = 5, /*!< System PLL input */
|
||
|
|
SYSCON_MAINCLKSRC_PLLOUT, /*!< System PLL output */
|
||
|
|
SYSCON_MAINCLKSRC_RTC /*!< RTC oscillator 32KHz output */
|
||
|
|
} CHIP_SYSCON_MAINCLKSRC_T;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Set main system clock source
|
||
|
|
* @param src : Clock source for main system
|
||
|
|
* @return Nothing
|
||
|
|
*/
|
||
|
|
void Chip_Clock_SetMainClockSource(CHIP_SYSCON_MAINCLKSRC_T src);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get main system clock source
|
||
|
|
* @return Clock source for main system
|
||
|
|
* @note
|
||
|
|
*/
|
||
|
|
CHIP_SYSCON_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return main clock rate
|
||
|
|
* @return main clock rate
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetMainClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Return system clock rate
|
||
|
|
* @return system clock rate
|
||
|
|
* @note This is the main clock rate divided by AHBCLKDIV.
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetSystemClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get UART base clock rate
|
||
|
|
* @return UART base clock rate
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_GetUARTBaseClockRate(void);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Get UART base clock rate using FRG
|
||
|
|
* @return Actual UART base clock rate
|
||
|
|
* @note It's recommended to set a base rate at least 16x the
|
||
|
|
* expected maximum UART transfer bit rate.
|
||
|
|
*/
|
||
|
|
uint32_t Chip_Clock_SetUARTBaseClockRate(uint32_t rate);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __CLOCK_5410X_H_ */
|