2013-01-08 21:05:02 +08:00
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/*
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2021-03-27 17:51:56 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2013-01-08 21:05:02 +08:00
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*
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2018-10-15 01:35:07 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2013-01-08 21:05:02 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2009-12-11 Bernard first version
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*/
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#ifndef __S3C24X0_H__
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#define __S3C24X0_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rtthread.h>
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/**
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* @addtogroup S3C24X0
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*/
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/*@{*/
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2021-03-27 17:51:56 +08:00
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// Memory control
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2013-01-08 21:05:02 +08:00
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#define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status
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#define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
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#define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
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#define BANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl
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#define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control
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#define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control
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#define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control
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#define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control
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#define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control
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#define REFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh
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#define BANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size
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#define MRSRB6 (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM
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#define MRSRB7 (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM
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// USB Host
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// INTERRUPT
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#define SRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status
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#define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control
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#define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control
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#define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control
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#define INTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status
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#define INTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset
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#define SUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending
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#define INTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask
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// DMA
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#define DISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
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#define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
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#define DIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
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#define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
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#define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
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#define DSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status
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#define DCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source
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#define DCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination
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#define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger
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#define DISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
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#define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
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#define DIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
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#define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
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#define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control
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#define DSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status
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#define DCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source
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#define DCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination
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#define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger
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#define DISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
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#define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
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#define DIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
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#define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
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#define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control
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#define DSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status
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#define DCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source
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#define DCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination
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#define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger
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#define DISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
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#define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
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#define DIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
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#define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
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#define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
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#define DSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status
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#define DCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source
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#define DCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination
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#define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger
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// CLOCK & POWER MANAGEMENT
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#define LOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter
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#define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control
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#define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control
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#define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control
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#define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control
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#define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control
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2021-03-27 17:51:56 +08:00
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#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
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2013-01-08 21:05:02 +08:00
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// LCD CONTROLLER
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#define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1
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#define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2
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#define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3
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#define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4
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#define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5
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#define LCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1
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#define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2
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#define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set
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#define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table
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#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table
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#define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table
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#define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode
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#define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette
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#define LCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending
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#define LCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source
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#define LCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask
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#define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control
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#define PALETTE 0x4d000400 //Palette start address
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// NAND flash
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#define NFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration
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#define NFCMD (*(volatile unsigned *)0x4e000004) //NADD Flash command
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#define NFADDR (*(volatile unsigned *)0x4e000008) //NAND Flash address
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#define NFDATA (*(volatile unsigned *)0x4e00000c) //NAND Flash data
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#define NFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status
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#define NFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC
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#define NFECC0 (*(volatile unsigned *)0x4e000014)
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#define NFECC1 (*(volatile unsigned *)0x4e000015)
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#define NFECC2 (*(volatile unsigned *)0x4e000016)
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// UART
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#define U0BASE (*(volatile unsigned *)0x50000000) //UART 0 Line control
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#define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control
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#define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control
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#define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control
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#define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control
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#define USTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status
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#define URXB0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status
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#define UFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status
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#define UMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status
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#define UBRD0 (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor
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#define U1BASE (*(volatile unsigned *)0x50004000) //UART 1 Line control
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#define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control
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#define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control
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#define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control
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#define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control
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#define USTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status
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#define URXB1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status
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#define UFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status
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#define UMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status
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#define UBRD1 (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor
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#define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control
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#define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control
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#define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control
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#define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control
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#define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control
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#define USTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status
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#define URXB2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status
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#define UFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status
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#define UMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status
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#define UBRD2 (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor
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#ifdef __BIG_ENDIAN
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#define UTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold
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#define URXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer
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#define UTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold
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#define URXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer
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#define UTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold
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#define URXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer
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#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
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#define RdURXH0() (*(volatile unsigned char *)0x50000027)
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#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
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#define RdURXH1() (*(volatile unsigned char *)0x50004027)
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#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
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#define RdURXH2() (*(volatile unsigned char *)0x50008027)
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#else //Little Endian
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#define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold
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#define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer
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#define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold
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#define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer
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#define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold
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#define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer
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#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
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#define RdURXH0() (*(volatile unsigned char *)0x50000024)
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#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
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#define RdURXH1() (*(volatile unsigned char *)0x50004024)
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#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
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#define RdURXH2() (*(volatile unsigned char *)0x50008024)
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#endif
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// PWM TIMER
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#define TCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration
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#define TCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration
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#define TCON (*(volatile unsigned *)0x51000008) //Timer control
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#define TCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0
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#define TCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0
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#define TCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0
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#define TCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1
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#define TCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1
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#define TCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1
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#define TCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2
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#define TCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2
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#define TCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2
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#define TCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3
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#define TCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3
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#define TCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3
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#define TCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4
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#define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4
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// Added for 2440
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#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only)
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#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0
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#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1
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#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register
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2013-01-08 21:05:02 +08:00
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// USB DEVICE
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#ifdef __BIG_ENDIAN
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#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address
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#define PWR_REG (*(volatile unsigned char *)0x52000147) //Power management
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#define EP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear
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#define USB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear
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#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable
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#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016f)
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#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte
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#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte
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#define INDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index
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#define MAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet
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#define EP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status
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#define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status
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#define IN_CSR2_REG (*(volatile unsigned char *)0x5200018b)
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#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status
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#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
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#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count
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#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f)
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#define EP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO
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#define EP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO
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#define EP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO
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#define EP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO
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#define EP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO
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#define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control
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#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter
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#define EP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter
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#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter
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#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213)
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#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217)
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#define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control
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#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter
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#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter
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#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter
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#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b)
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#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f)
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#define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control
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#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter
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#define EP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter
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#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter
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#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253)
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#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257)
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#define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control
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#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter
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#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter
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#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter
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#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b)
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#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f)
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#else // Little Endian
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#define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address
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#define PWR_REG (*(volatile unsigned char *)0x52000144) //Power management
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#define EP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear
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#define USB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear
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#define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable
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#define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016c)
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#define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte
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#define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte
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#define INDEX_REG (*(volatile unsigned char *)0x52000178) //Register index
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#define MAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet
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#define EP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status
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#define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status
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#define IN_CSR2_REG (*(volatile unsigned char *)0x52000188)
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#define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status
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#define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
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#define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count
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#define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c)
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#define EP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO
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#define EP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO
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#define EP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO
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#define EP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO
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#define EP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO
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#define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control
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#define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter
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#define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter
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#define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter
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#define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210)
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#define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214)
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#define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control
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#define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter
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#define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter
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#define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter
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#define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228)
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#define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c)
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#define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control
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#define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter
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#define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter
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#define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter
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#define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250)
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#define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254)
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#define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control
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#define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter
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#define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter
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#define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter
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#define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268)
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#define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c)
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|
#endif // __BIG_ENDIAN
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// WATCH DOG TIMER
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#define WTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode
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#define WTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data
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#define WTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count
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// IIC
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|
#define IICCON (*(volatile unsigned *)0x54000000) //IIC control
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#define IICSTAT (*(volatile unsigned *)0x54000004) //IIC status
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#define IICADD (*(volatile unsigned *)0x54000008) //IIC address
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#define IICDS (*(volatile unsigned *)0x5400000c) //IIC data shift
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// IIS
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|
#define IISCON (*(volatile unsigned *)0x55000000) //IIS Control
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#define IISMOD (*(volatile unsigned *)0x55000004) //IIS Mode
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#define IISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler
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#define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control
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|
|
#ifdef __BIG_ENDIAN
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|
|
#define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry
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#else //Little Endian
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|
|
#define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry
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#endif
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|
// I/O PORT
|
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|
|
#define GPACON (*(volatile unsigned *)0x56000000) //Port A control
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|
#define GPADAT (*(volatile unsigned *)0x56000004) //Port A data
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#define GPBCON (*(volatile unsigned *)0x56000010) //Port B control
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#define GPBDAT (*(volatile unsigned *)0x56000014) //Port B data
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|
#define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B
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#define GPCCON (*(volatile unsigned *)0x56000020) //Port C control
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|
#define GPCDAT (*(volatile unsigned *)0x56000024) //Port C data
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|
|
#define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C
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|
#define GPDCON (*(volatile unsigned *)0x56000030) //Port D control
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|
#define GPDDAT (*(volatile unsigned *)0x56000034) //Port D data
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|
#define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D
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#define GPECON (*(volatile unsigned *)0x56000040) //Port E control
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#define GPEDAT (*(volatile unsigned *)0x56000044) //Port E data
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|
#define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E
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#define GPFCON (*(volatile unsigned *)0x56000050) //Port F control
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#define GPFDAT (*(volatile unsigned *)0x56000054) //Port F data
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|
#define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F
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#define GPGCON (*(volatile unsigned *)0x56000060) //Port G control
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#define GPGDAT (*(volatile unsigned *)0x56000064) //Port G data
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|
#define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G
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#define GPHCON (*(volatile unsigned *)0x56000070) //Port H control
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|
#define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data
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|
|
#define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
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|
2021-03-27 17:51:56 +08:00
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|
|
#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control
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|
|
#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data
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|
|
#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J
|
2013-01-08 21:05:02 +08:00
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|
|
#define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
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|
|
#define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
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|
#define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0
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|
|
#define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1
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|
#define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2
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|
|
#define EINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved
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|
#define EINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved
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|
#define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2
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#define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3
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|
|
#define EINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask
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#define EINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending
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|
#define GSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status
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|
#define GSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32410000)
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#define GSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type
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#define GSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode
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#define GSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode
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// RTC
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|
#ifdef __BIG_ENDIAN
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|
|
#define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control
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|
|
#define TICNT (*(volatile unsigned char *)0x57000047) //Tick time count
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|
#define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control
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|
|
#define ALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second
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|
|
#define ALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute
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|
#define ALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour
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|
|
#define ALMDATE (*(volatile unsigned char *)0x57000063) //Alarm day <-- May 06, 2002 SOP
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|
#define ALMMON (*(volatile unsigned char *)0x57000067) //Alarm month
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|
#define ALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year
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|
|
#define RTCRST (*(volatile unsigned char *)0x5700006f) //RTC ound eset
|
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|
|
#define BCDSEC (*(volatile unsigned char *)0x57000073) //BCD second
|
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|
|
#define BCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute
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|
|
#define BCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour
|
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|
|
#define BCDDATE (*(volatile unsigned char *)0x5700007f) //BCD day <-- May 06, 2002 SOP
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|
|
#define BCDDAY (*(volatile unsigned char *)0x57000083) //BCD date <-- May 06, 2002 SOP
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|
|
#define BCDMON (*(volatile unsigned char *)0x57000087) //BCD month
|
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|
|
#define BCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year
|
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|
|
#else //Little Endian
|
|
|
|
|
#define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control
|
|
|
|
|
#define TICNT (*(volatile unsigned char *)0x57000044) //Tick time count
|
|
|
|
|
#define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control
|
|
|
|
|
#define ALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second
|
|
|
|
|
#define ALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute
|
|
|
|
|
#define ALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour
|
|
|
|
|
#define ALMDATE (*(volatile unsigned char *)0x57000060) //Alarm day <-- May 06, 2002 SOP
|
|
|
|
|
#define ALMMON (*(volatile unsigned char *)0x57000064) //Alarm month
|
|
|
|
|
#define ALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year
|
|
|
|
|
#define RTCRST (*(volatile unsigned char *)0x5700006c) //RTC ound eset
|
|
|
|
|
#define BCDSEC (*(volatile unsigned char *)0x57000070) //BCD second
|
|
|
|
|
#define BCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute
|
|
|
|
|
#define BCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour
|
|
|
|
|
#define BCDDATE (*(volatile unsigned char *)0x5700007c) //BCD day <-- May 06, 2002 SOP
|
|
|
|
|
#define BCDDAY (*(volatile unsigned char *)0x57000080) //BCD date <-- May 06, 2002 SOP
|
|
|
|
|
#define BCDMON (*(volatile unsigned char *)0x57000084) //BCD month
|
|
|
|
|
#define BCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year
|
|
|
|
|
#endif //RTC
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// ADC
|
|
|
|
|
#define ADCCON (*(volatile unsigned *)0x58000000) //ADC control
|
|
|
|
|
#define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control
|
|
|
|
|
#define ADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay
|
|
|
|
|
#define ADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0
|
|
|
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#define ADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1
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// SPI
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#define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
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#define SPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
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#define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
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#define SPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud ate prescaler
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#define SPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
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#define SPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
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#define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
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#define SPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status
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#define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
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#define SPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud ate prescaler
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#define SPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data
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#define SPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data
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// SD Interface
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#define SDICON (*(volatile unsigned *)0x5a000000) //SDI control
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#define SDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud ate prescaler
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#define SDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument
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#define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
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#define SDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status
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#define SDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI esponse 0
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#define SDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI esponse 1
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#define SDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI esponse 2
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#define SDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI esponse 3
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#define SDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer
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#define SDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size
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#define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control
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#define SDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data emain counter
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#define SDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status
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#define SDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status
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#define SDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask
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#ifdef __BIG_ENDIAN /* edited for 2440A */
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#define SDIDAT (*(volatile unsigned *)0x5a00004c)
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#else // Little Endian
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2021-03-27 17:51:56 +08:00
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#define SDIDAT (*(volatile unsigned *)0x5a000040)
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2013-01-08 21:05:02 +08:00
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#endif //SD Interface
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// PENDING BIT
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#define INTEINT0 (0)
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#define INTEINT1 (1)
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#define INTEINT2 (2)
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#define INTEINT3 (3)
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#define INTEINT4_7 (4)
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#define INTEINT8_23 (5)
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#define INTNOTUSED6 (6)
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#define INTBAT_FLT (7)
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#define INTTICK (8)
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#define INTWDT (9)
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#define INTTIMER0 (10)
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#define INTTIMER1 (11)
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#define INTTIMER2 (12)
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#define INTTIMER3 (13)
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#define INTTIMER4 (14)
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#define INTUART2 (15)
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#define INTLCD (16)
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#define INTDMA0 (17)
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#define INTDMA1 (18)
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#define INTDMA2 (19)
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#define INTDMA3 (20)
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#define INTSDI (21)
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#define INTSPI0 (22)
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#define INTUART1 (23)
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//#define INTNOTUSED24 (24)
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#define INTNIC (24)
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#define INTUSBD (25)
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#define INTUSBH (26)
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#define INTIIC (27)
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#define INTUART0 (28)
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#define INTSPI1 (29)
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#define INTRTC (30)
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#define INTADC (31)
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#define BIT_ALLMSK (0xffffffff)
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#define BIT_SUB_ALLMSK (0x7ff)
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#define INTSUB_ADC (10)
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#define INTSUB_TC (9)
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#define INTSUB_ERR2 (8)
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#define INTSUB_TXD2 (7)
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#define INTSUB_RXD2 (6)
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#define INTSUB_ERR1 (5)
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#define INTSUB_TXD1 (4)
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#define INTSUB_RXD1 (3)
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#define INTSUB_ERR0 (2)
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#define INTSUB_TXD0 (1)
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#define INTSUB_RXD0 (0)
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#define BIT_SUB_ADC (0x1<<10)
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#define BIT_SUB_TC (0x1<<9)
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#define BIT_SUB_ERR2 (0x1<<8)
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#define BIT_SUB_TXD2 (0x1<<7)
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#define BIT_SUB_RXD2 (0x1<<6)
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#define BIT_SUB_ERR1 (0x1<<5)
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#define BIT_SUB_TXD1 (0x1<<4)
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#define BIT_SUB_RXD1 (0x1<<3)
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#define BIT_SUB_ERR0 (0x1<<2)
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#define BIT_SUB_TXD0 (0x1<<1)
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#define BIT_SUB_RXD0 (0x1<<0)
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#define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;}
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//Wait until INTPND is changed for the case that the ISR is very short.
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2021-03-27 17:51:56 +08:00
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#define INTGLOBAL 32
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2013-01-08 21:05:02 +08:00
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/*****************************/
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/* CPU Mode */
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/*****************************/
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2021-03-27 17:51:56 +08:00
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#define USERMODE 0x10
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#define FIQMODE 0x11
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#define IRQMODE 0x12
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#define SVCMODE 0x13
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#define ABORTMODE 0x17
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#define UNDEFMODE 0x1b
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#define MODEMASK 0x1f
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#define NOINT 0xc0
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2013-01-08 21:05:02 +08:00
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struct rt_hw_register
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{
|
2021-03-27 17:51:56 +08:00
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rt_uint32_t r0;
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rt_uint32_t r1;
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rt_uint32_t r2;
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rt_uint32_t r3;
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rt_uint32_t r4;
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rt_uint32_t r5;
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rt_uint32_t r6;
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rt_uint32_t r7;
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rt_uint32_t r8;
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rt_uint32_t r9;
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rt_uint32_t r10;
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rt_uint32_t fp;
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rt_uint32_t ip;
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rt_uint32_t sp;
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rt_uint32_t lr;
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rt_uint32_t pc;
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rt_uint32_t cpsr;
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rt_uint32_t ORIG_r0;
|
2013-01-08 21:05:02 +08:00
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};
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#ifdef __cplusplus
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}
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#endif
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/*@}*/
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#endif
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