2022-11-10 22:22:48 +08:00
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fsdio_dma.c
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* Date: 2022-06-01 14:21:41
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* LastEditTime: 2022-06-01 14:21:42
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2023-05-11 10:25:21 +08:00
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* Description: This file is for DMA related function implementation
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2022-11-10 22:22:48 +08:00
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.1 zhugengyu 2022/6/6 modify according to tech manual.
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*/
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/***************************** Include Files *********************************/
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#include <string.h>
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#include "fio.h"
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#include "fdebug.h"
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#include "fassert.h"
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#include "ftypes.h"
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#include "fsdio_hw.h"
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#include "fsdio.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FSDIO_DEBUG_TAG "FSDIO-DMA"
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#define FSDIO_ERROR(format, ...) FT_DEBUG_PRINT_E(FSDIO_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FSDIO_WARN(format, ...) FT_DEBUG_PRINT_W(FSDIO_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FSDIO_INFO(format, ...) FT_DEBUG_PRINT_I(FSDIO_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FSDIO_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSDIO_DEBUG_TAG, format, ##__VA_ARGS__)
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/************************** Function Prototypes ******************************/
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extern FError FSdioTransferCmd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
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extern FError FSdioPollWaitBusyCard(FSdio *const instance_p);
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2022-11-10 22:22:48 +08:00
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/*****************************************************************************/
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/**
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* @name: FSdioDumpDMADescriptor
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* @msg: dump DMA descriptor list
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* @return {*}
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* @param {FSdio} *instance_p, instance of controller
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* @param {u32} desc_in_use, max index of descriptor in use
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*/
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static void FSdioDumpDMADescriptor(FSdio *const instance_p, u32 desc_in_use)
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{
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u32 loop;
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volatile FSdioIDmaDesc *cur_desc = NULL;
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if (instance_p->desc_list.first_desc)
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{
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for (loop = 0; loop < desc_in_use; loop++)
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{
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cur_desc = &(instance_p->desc_list.first_desc[loop]);
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FSDIO_DEBUG("descriptor@%p", cur_desc);
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FSDIO_DEBUG("\tattribute: 0x%x", cur_desc->attribute);
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FSDIO_DEBUG("\tnon1: 0x%x", cur_desc->non1);
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FSDIO_DEBUG("\tlen: 0x%x", cur_desc->len);
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FSDIO_DEBUG("\tnon2: 0x%x", cur_desc->non2);
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FSDIO_DEBUG("\taddr_lo: 0x%x", cur_desc->addr_lo);
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FSDIO_DEBUG("\taddr_hi: 0x%x", cur_desc->addr_hi);
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FSDIO_DEBUG("\tdesc_lo: 0x%x", cur_desc->desc_lo);
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FSDIO_DEBUG("\tdesc_hi: 0x%x", cur_desc->desc_hi);
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}
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}
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}
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/**
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* @name: FSdioSetupDMADescriptor
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* @msg: setup DMA descriptor list before do transcation
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* @return {FError} FSDIO_SUCCESS if setup success
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* @param {FSdio} *instance_p, instance of controller
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* @param {FSdioData} *data_p, data in transcation
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*/
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static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p)
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{
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FASSERT(data_p);
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FASSERT(instance_p->desc_list.first_desc);
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u32 loop;
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u32 buf_num = data_p->datalen / data_p->blksz +
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((data_p->datalen % data_p->blksz) ? 1U : 0U);
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volatile FSdioIDmaDesc *cur_desc = NULL;
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uintptr buff_addr = 0U;
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uintptr desc_addr = 0U;
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boolean is_first = TRUE;
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boolean is_last = FALSE;
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if (buf_num > instance_p->desc_list.desc_num)
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{
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FSDIO_ERROR("Descriptor is too short to transfer %d < %d.",
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instance_p->desc_list.desc_num, buf_num);
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return FSDIO_ERR_SHORT_BUF;
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}
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memset((void *)instance_p->desc_list.first_desc, 0,
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sizeof(FSdioIDmaDesc) * instance_p->desc_list.desc_num);
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2023-05-11 10:25:21 +08:00
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FSDIO_INFO("%d of descriptor is in using.", buf_num);
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2022-11-10 22:22:48 +08:00
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for (loop = 0U; loop < buf_num; loop++)
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{
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cur_desc = &(instance_p->desc_list.first_desc[loop]);
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is_first = (0U == loop) ? TRUE : FALSE;
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is_last = ((buf_num - 1U) == loop) ? TRUE : FALSE;
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/* set properity of descriptor entry */
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cur_desc->attribute = FSDIO_IDMAC_DES0_CH | FSDIO_IDMAC_DES0_OWN; /* descriptor list in chain, and set OWN bit */
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cur_desc->attribute |= (is_first) ? FSDIO_IDMAC_DES0_FD : 0; /* is it the first entry ? */
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cur_desc->attribute |= (is_last) ? (FSDIO_IDMAC_DES0_LD | FSDIO_IDMAC_DES0_ER) : 0; /* is it the last entry ? */
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/* set data length in transfer */
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cur_desc->non1 = 0U;
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cur_desc->len = FSDIO_IDMAC_DES2_BUF1_SIZE(data_p->blksz) | FSDIO_IDMAC_DES2_BUF2_SIZE(0U);
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/* set data buffer for transfer */
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buff_addr = (uintptr)data_p->buf + (uintptr)(loop * data_p->blksz);
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if (buff_addr % data_p->blksz) /* make sure buffer aligned and not cross page boundary */
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{
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FSDIO_ERROR("Data buffer 0x%x do not align.", buff_addr);
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return FSDIO_ERR_DMA_BUF_UNALIGN;
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}
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2022-11-10 22:22:48 +08:00
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#ifdef __aarch64__
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cur_desc->addr_hi = UPPER_32_BITS(buff_addr);
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cur_desc->addr_lo = LOWER_32_BITS(buff_addr);
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#else
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cur_desc->addr_hi = 0U;
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cur_desc->addr_lo = (u32)(buff_addr);
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#endif
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/* set address of next descriptor entry, NULL for last entry */
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desc_addr = is_last ? 0U : (uintptr)&instance_p->desc_list.first_desc[loop + 1];
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if (desc_addr % sizeof(FSdioIDmaDesc)) /* make sure dma descriptor aligned and not cross page boundary */
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{
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FSDIO_ERROR("dma descriptor 0x%x do not align.", desc_addr);
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return FSDIO_ERR_DMA_BUF_UNALIGN;
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}
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2022-11-10 22:22:48 +08:00
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#ifdef __aarch64__
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cur_desc->desc_hi = UPPER_32_BITS(desc_addr);
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cur_desc->desc_lo = LOWER_32_BITS(desc_addr);
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#else
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cur_desc->desc_hi = 0U;
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cur_desc->desc_lo = (u32)(desc_addr);
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#endif
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}
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/* flush cache of descripor list and transfer buffer */
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FSDIO_DATA_BARRIER();
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FSdioDumpDMADescriptor(instance_p, buf_num);
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return FSDIO_SUCCESS;
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}
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/**
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* @name: FSdioDMATransferData
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* @msg:
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* @return {*}
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* @param {FSdio} *instance_p
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* @param {FSdioData} *data_p
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*/
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static FError FSdioDMATransferData(FSdio *const instance_p, FSdioData *data_p)
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{
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FASSERT(data_p);
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FError ret = FSDIO_SUCCESS;
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uintptr base_addr = instance_p->config.base_addr;
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/* enable related interrupt */
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FSdioSetInterruptMask(instance_p, FSDIO_GENERAL_INTR, FSDIO_INTS_DATA_MASK, TRUE);
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FSdioSetInterruptMask(instance_p, FSDIO_IDMA_INTR, FSDIO_DMAC_INTS_MASK, TRUE);
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/* fill transfer buffer to DMA descriptor */
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ret = FSdioSetupDMADescriptor(instance_p, data_p);
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if (FSDIO_SUCCESS != ret)
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{
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return ret;
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}
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FSDIO_DATA_BARRIER();
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FSDIO_INFO("Descriptor@%p, trans bytes: %d, block size: %d",
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instance_p->desc_list.first_desc,
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data_p->datalen,
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data_p->blksz);
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/* set transfer info to register */
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FSdioSetDescriptor(base_addr, (uintptr)(instance_p->desc_list.first_desc));
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FSdioSetTransBytes(base_addr, data_p->datalen);
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FSdioSetBlockSize(base_addr, data_p->blksz);
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return ret;
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}
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/**
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* @name: FSdioDMATransfer
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* @msg: Start command and data transfer in DMA mode
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* @return {FError} FSDIO_SUCCESS if transfer success, otherwise failed
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* @param {FSdio} *instance_p, SDIO controller instance
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* @param {FSdioCmdData} *cmd_data_p, contents of transfer command and data
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*/
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FError FSdioDMATransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
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{
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FASSERT(instance_p);
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FASSERT(cmd_data_p);
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FError ret = FSDIO_SUCCESS;
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uintptr base_addr = instance_p->config.base_addr;
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cmd_data_p->success = FALSE; /* reset cmd transfer status */
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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FSDIO_ERROR("Device is not yet initialized!!!");
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return FSDIO_ERR_NOT_INIT;
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}
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if (FSDIO_IDMA_TRANS_MODE != instance_p->config.trans_mode)
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{
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FSDIO_ERROR("Device is not configure in DMA transfer mode.");
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return FSDIO_ERR_INVALID_STATE;
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}
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/* for removable media, check if card exists */
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if ((FALSE == instance_p->config.non_removable) &&
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(FALSE == FSdioCheckIfCardExists(base_addr)))
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{
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FSDIO_ERROR("Card is not detected !!!");
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return FSDIO_ERR_NO_CARD;
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}
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2023-05-11 10:25:21 +08:00
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/* wait previous command finished and card not busy */
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ret = FSdioPollWaitBusyCard(instance_p);
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if (FSDIO_SUCCESS != ret)
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{
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return ret;
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}
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FSDIO_WRITE_REG(base_addr, FSDIO_RAW_INTS_OFFSET, 0xffffe);
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/* reset fifo and DMA before transfer */
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ret = FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET);
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if (FSDIO_SUCCESS != ret)
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{
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return ret;
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}
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/* enable use of DMA */
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FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_USE_INTERNAL_DMAC);
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FSDIO_SET_BIT(base_addr, FSDIO_BUS_MODE_OFFSET, FSDIO_BUS_MODE_DE);
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if (NULL != cmd_data_p->data_p) /* transfer data */
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{
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ret = FSdioDMATransferData(instance_p,
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cmd_data_p->data_p);
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}
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if (FSDIO_SUCCESS == ret) /* transfer command */
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{
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ret = FSdioTransferCmd(instance_p, cmd_data_p);
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}
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return ret;
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}
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/**
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* @name: FSdioPollWaitDMAEnd
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* @msg: Wait DMA transfer finished by poll
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* @return {FError} FSDIO_SUCCESS if wait success, otherwise wait failed
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* @param {FSdio} *instance_p, SDIO controller instance
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* @param {FSdioCmdData} *cmd_data_p, contents of transfer command and data
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* @param {FSdioRelaxHandler} relax, handler of relax when wait busy
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*/
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2023-05-11 10:25:21 +08:00
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FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
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2022-11-10 22:22:48 +08:00
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{
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FASSERT(instance_p);
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FASSERT(cmd_data_p);
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FError ret = FSDIO_SUCCESS;
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u32 reg_val;
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int delay;
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const boolean read = cmd_data_p->flag & FSDIO_CMD_FLAG_READ_DATA;
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uintptr base_addr = instance_p->config.base_addr;
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2023-05-11 10:25:21 +08:00
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const u32 wait_bits = (NULL == cmd_data_p->data_p) ? FSDIO_INT_CMD_BIT : (FSDIO_INT_CMD_BIT | FSDIO_INT_DTO_BIT);
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2022-11-10 22:22:48 +08:00
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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2023-05-11 10:25:21 +08:00
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FSDIO_ERROR("Device is not yet initialized!!!");
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2022-11-10 22:22:48 +08:00
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return FSDIO_ERR_NOT_INIT;
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}
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if (FSDIO_IDMA_TRANS_MODE != instance_p->config.trans_mode)
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{
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2023-05-11 10:25:21 +08:00
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FSDIO_ERROR("Device is not configure in DMA transfer mode.");
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2022-11-10 22:22:48 +08:00
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return FSDIO_ERR_INVALID_STATE;
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}
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2023-05-11 10:25:21 +08:00
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/* wait command done or data timeout */
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2022-11-10 22:22:48 +08:00
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delay = FSDIO_TIMEOUT;
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do
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{
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reg_val = FSdioGetRawStatus(base_addr);
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2023-05-11 10:25:21 +08:00
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if (delay % 1000 == 0)
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{
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FSDIO_DEBUG("reg_val = 0x%x", reg_val);
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}
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if (instance_p->relax_handler)
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{
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instance_p->relax_handler();
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}
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2022-11-10 22:22:48 +08:00
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}
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2023-05-11 10:25:21 +08:00
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while (((wait_bits & reg_val) != wait_bits) && (--delay > 0));
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/* clear status to ack data done */
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FSdioClearRawStatus(base_addr);
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2022-11-10 22:22:48 +08:00
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2023-05-11 10:25:21 +08:00
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if (((wait_bits & reg_val) != wait_bits) && (delay <= 0))
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2022-11-10 22:22:48 +08:00
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{
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2023-05-11 10:25:21 +08:00
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FSDIO_ERROR("Wait cmd done timeout, raw ints: 0x%x.", reg_val);
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2022-11-10 22:22:48 +08:00
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return FSDIO_ERR_CMD_TIMEOUT;
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}
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if (NULL != cmd_data_p->data_p) /* wait data transfer done or timeout */
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{
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/* invalidate cache of transfer buffer */
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if (read)
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{
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2023-05-11 10:25:21 +08:00
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FSDIO_DATA_BARRIER();
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2022-11-10 22:22:48 +08:00
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}
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}
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if (FSDIO_SUCCESS == ret)
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{
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ret = FSdioGetCmdResponse(instance_p, cmd_data_p);
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}
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return ret;
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}
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/**
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* @name: FSdioSetIDMAList
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* @msg: Setup DMA descriptor for SDIO controller instance
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* @return {FError} FSDIO_SUCCESS if setup done, otherwise failed
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* @param {FSdio} *instance_p, SDIO controller instance
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* @param {volatile FSdioIDmaDesc} *desc, first item in DMA descriptor lists
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* @param {u32} desc_num, number of items in DMA descriptor lists
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*/
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FError FSdioSetIDMAList(FSdio *const instance_p, volatile FSdioIDmaDesc *desc, u32 desc_num)
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{
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FASSERT(instance_p);
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FError ret = FSDIO_SUCCESS;
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uintptr base_addr = instance_p->config.base_addr;
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if (FT_COMPONENT_IS_READY != instance_p->is_ready)
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{
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2023-05-11 10:25:21 +08:00
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FSDIO_ERROR("Device is not yet initialized!!!");
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2022-11-10 22:22:48 +08:00
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return FSDIO_ERR_NOT_INIT;
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}
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if (FSDIO_IDMA_TRANS_MODE != instance_p->config.trans_mode)
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{
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2023-05-11 10:25:21 +08:00
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FSDIO_ERROR("Device is not configure in DMA transfer mode.");
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2022-11-10 22:22:48 +08:00
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return FSDIO_ERR_INVALID_STATE;
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}
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instance_p->desc_list.first_desc = desc;
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instance_p->desc_list.desc_num = desc_num;
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return ret;
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}
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