564 lines
16 KiB
C
564 lines
16 KiB
C
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/* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* ===========================================================================================
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*
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* Filename: hal_pwm.c
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*
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* Description: spi driver core hal,be used by drv_pwm.c
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*
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* Version: Melis3.0
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* Create: 2019-12-23
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* Revision: none
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* Compiler: GCC:version 9.2.1 20170904 (release),ARM/embedded-7-branch revision 255204
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*
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* Author: liuyus@allwinnertech.com
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* Organization: SWC-BPD
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* Last Modified: 2019-12-31 17:55
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*
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* ===========================================================================================
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*/
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#include <hal_log.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <hal_clk.h>
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#include <hal_reset.h>
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#include <sunxi_hal_common.h>
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#include <sunxi_hal_pwm.h>
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#include "sunxi/clk.h"
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#include <hal_cfg.h>
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#include <script.h>
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// #include <standby/standby.h>
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hal_pwm_t sunxi_pwm;
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static int pwm_init = 0;
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#define SET_REG_VAL(reg_val, shift, width, set_val) ((reg_val & ~((-1UL) >> (32 - width) << shift)) | (set_val << shift))
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#define pwm_do_div(n,base) ({ \
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u32 __base = (base); \
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u32 __rem; \
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__rem = ((u64)(n)) % __base; \
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(n) = ((u64)(n)) / __base; \
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if (__rem > __base / 2) \
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++(n); \
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__rem; \
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})
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/************** config *************************/
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/*
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* pwm_set_clk_src(): pwm clock source selection
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*
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* @channel_in: pwm channel number
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* pwm01 pwm23 pwm45 pwm67 pwm89
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*
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* @clk_src: The clock you want to set
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* 0:OSC24M 1:APB1
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*/
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void hal_pwm_clk_src_set(uint32_t channel_in, hal_pwm_clk_src clk_src)
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{
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unsigned long reg_addr = PWM_BASE + PWM_PCCR_BASE;
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uint32_t reg_val;
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uint32_t channel = channel_in / 2;
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reg_addr += 4 * channel;
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/*set clock source OSC24M or apb1*/
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reg_val = hal_readl(reg_addr);
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reg_val = SET_REG_VAL(reg_val, PWM_CLK_SRC_SHIFT, PWM_CLK_SRC_WIDTH, clk_src);
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hal_writel(reg_val, reg_addr);
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}
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/*
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* pwm_clk_div_m(): pwm clock divide
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*
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* @div_m: 1 2 4 8 16 32 64 128 256
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*/
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void hal_pwm_clk_div_m(uint32_t channel_in, uint32_t div_m)
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{
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unsigned long reg_addr = PWM_BASE + PWM_PCCR_BASE;
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uint32_t reg_val;
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uint32_t channel = channel_in / 2;
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reg_addr += 4 * channel;
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/*set clock div_m*/
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reg_val = hal_readl(reg_addr);
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reg_val = SET_REG_VAL(reg_val, PWM_DIV_M_SHIFT, PWM_DIV_M_WIDTH, div_m);
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hal_writel(reg_val, reg_addr);
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}
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void hal_pwm_prescal_set(uint32_t channel_in, uint32_t prescal)
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{
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unsigned long reg_addr = PWM_BASE + PWM_PCR;
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uint32_t reg_val;
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uint32_t channel = channel_in;
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reg_addr += 0x20 * channel;
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/*set prescal*/
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reg_val = hal_readl(reg_addr);
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reg_val = SET_REG_VAL(reg_val, PWM_PRESCAL_SHIFT, PWM_PRESCAL_WIDTH, prescal);
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hal_writel(reg_val, reg_addr);
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}
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/* active cycles */
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void hal_pwm_set_active_cycles(uint32_t channel_in, uint32_t active_cycles) //64
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{
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unsigned long reg_addr = PWM_BASE + PWM_PPR ;
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uint32_t reg_val;
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uint32_t channel = channel_in;
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reg_addr += 0x20 * channel;
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/*set active*/
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reg_val = hal_readl(reg_addr);
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reg_val = SET_REG_VAL(reg_val, PWM_ACTIVE_CYCLES_SHIFT, PWM_ACTIVE_CYCLES_WIDTH, active_cycles);
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hal_writel(reg_val, reg_addr);
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}
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/* entire cycles */
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void hal_pwm_set_period_cycles(uint32_t channel_in, uint32_t period_cycles)
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{
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unsigned long reg_addr = PWM_BASE + PWM_PPR ;
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uint32_t reg_val;
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uint32_t channel = channel_in;
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reg_addr += 0x20 * channel;
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/*set clock BYPASS*/
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reg_val = hal_readl(reg_addr);
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reg_val = SET_REG_VAL(reg_val, PWM_PERIOD_SHIFT, PWM_PERIOD_WIDTH, period_cycles);
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hal_writel(reg_val, reg_addr);
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}
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static uint32_t get_pccr_reg_offset(uint32_t channel)
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{
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uint32_t val;
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switch (channel)
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{
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case 0:
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case 1:
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return PWM_PCCR01;
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break;
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case 2:
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case 3:
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return PWM_PCCR23;
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break;
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case 4:
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case 5:
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return PWM_PCCR45;
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break;
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case 6:
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case 7:
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return PWM_PCCR67;
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break;
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default :
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PWM_ERR("channel is error \n");
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return PWM_PCCR01;
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break;
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}
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}
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/************ enable **************/
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void hal_pwm_enable_clk_gating(uint32_t channel_in)
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{
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unsigned long reg_addr = PWM_BASE + PWM_PCGR;
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uint32_t reg_val;
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uint32_t channel = channel_in / 2;
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/*enable clk_gating*/
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reg_addr += 4 * channel;
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reg_val = hal_readl(reg_addr);
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reg_val = SET_REG_VAL(reg_val, PWM_CLK_GATING_SHIFT, PWM_CLK_GATING_WIDTH, 1);
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hal_writel(reg_val, reg_addr);
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}
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void hal_pwm_enable_controller(uint32_t channel_in)
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{
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unsigned long reg_addr = PWM_BASE + PWM_PER;
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uint32_t reg_val;
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reg_val = readl(reg_addr);
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reg_val |= 1 << channel_in;
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writel(reg_val, reg_addr);
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}
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/************ disable **************/
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void hal_pwm_disable_controller(uint32_t channel_in)
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{
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unsigned long reg_val;
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unsigned long reg_addr = PWM_BASE + PWM_PER;
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reg_val = readl(reg_addr);
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reg_val |= 1 << channel_in;
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writel(reg_val, reg_addr);
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}
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/*************** polarity *****************/
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void hal_pwm_porality(uint32_t channel_in, hal_pwm_polarity polarity)
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{
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uint32_t reg_val;
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unsigned long reg_addr = PWM_BASE + PWM_PCR;
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uint32_t channel = channel_in;
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reg_addr += 0x20 * channel;
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/*set polarity*/
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reg_val = hal_readl(reg_addr);
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reg_val = SET_REG_VAL(reg_val, PWM_ACT_STA_SHIFT, PWM_ACT_STA_WIDTH, polarity);
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hal_writel(reg_val, reg_addr);
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}
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static int hal_pwm_pinctrl_init(hal_pwm_t sunxi_pwm, int channel)
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{
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user_gpio_set_t gpio_cfg = {0};
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char pwm_name[16];
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int count, ret;
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sprintf(pwm_name, "pwm%d", channel);
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count = Hal_Cfg_GetGPIOSecKeyCount(pwm_name);
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if (!count)
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{
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PWM_ERR("[pwm%d] not support in sys_config\n", channel);
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return -1;
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}
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Hal_Cfg_GetGPIOSecData(pwm_name, &gpio_cfg, count);
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sunxi_pwm.pin[channel] = (gpio_cfg.port - 1) * 32 + gpio_cfg.port_num;
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sunxi_pwm.enable_muxsel[channel] = gpio_cfg.mul_sel;
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ret = hal_gpio_pinmux_set_function(sunxi_pwm.pin[channel], sunxi_pwm.enable_muxsel[channel]);
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if (ret)
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{
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PWM_ERR("[pwm%d] PIN%u set function failed! return %d\n", channel, sunxi_pwm.pin[channel], ret);
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return -1;
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}
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ret = hal_gpio_set_driving_level(sunxi_pwm.pin[channel], gpio_cfg.drv_level);
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if (ret)
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{
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PWM_ERR("[spi%d] PIN%u set driving level failed! return %d\n", channel, gpio_cfg.drv_level, ret);
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return -1;
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}
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if (gpio_cfg.pull)
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{
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return hal_gpio_set_pull(sunxi_pwm.pin[channel], gpio_cfg.pull);
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}
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return 0;
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}
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static int hal_pwm_pinctrl_exit(hal_pwm_t sunxi_pwm, uint32_t channel)
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{
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if (sunxi_pwm.pin[channel]) //sys_config
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{
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return hal_gpio_pinmux_set_function(sunxi_pwm.pin[channel], 0); //gpio_in
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}
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else
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{
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return hal_gpio_pinmux_set_function(pwm_gpio[channel].pwm_pin, 0);
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}
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}
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/****the function provide for pwm driverr******************************************/
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pwm_status_t hal_pwm_init(void)
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{
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PWM_INFO("pwm init start");
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if (pwm_init)
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{
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pwm_init++;
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return 0;
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}
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sunxi_pwm.pwm_clk_type = SUNXI_PWM_CLK_TYPE;
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sunxi_pwm.pwm_bus_clk_id = SUNXI_PWM_CLK_ID;
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sunxi_pwm.pwm_reset_type = SUNXI_PWM_RESET_TYPE;
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sunxi_pwm.pwm_reset_id = SUNXI_PWM_RESET_ID;
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if (!sunxi_pwm.pwm_reset)
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{
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sunxi_pwm.pwm_reset = hal_reset_control_get(sunxi_pwm.pwm_reset_type, sunxi_pwm.pwm_reset_id);
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}
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hal_reset_control_deassert(sunxi_pwm.pwm_reset);
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if (!sunxi_pwm.pwm_bus_clk)
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{
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sunxi_pwm.pwm_bus_clk = hal_clock_get(sunxi_pwm.pwm_clk_type, sunxi_pwm.pwm_bus_clk_id);
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PWM_INFO("pwm_bus_clk name:%s", sunxi_pwm.pwm_bus_clk->name);
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}
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if (hal_clock_enable(sunxi_pwm.pwm_bus_clk))
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{
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return -1;
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}
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#ifdef CONFIG_STANDBY
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register_pm_dev_notify(hal_pwm_suspend, hal_pwm_resume, NULL);
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#endif
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PWM_INFO("pwm init end ");
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pwm_init++;
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|
return 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
pwm_status_t hal_pwm_deinit(void)
|
|||
|
|
{
|
|||
|
|
if (pwm_init)
|
|||
|
|
{
|
|||
|
|
pwm_init--;
|
|||
|
|
if (!pwm_init)
|
|||
|
|
{
|
|||
|
|
hal_reset_control_assert(sunxi_pwm.pwm_reset);
|
|||
|
|
hal_reset_control_put(sunxi_pwm.pwm_reset);
|
|||
|
|
|
|||
|
|
hal_clock_disable(sunxi_pwm.pwm_bus_clk);
|
|||
|
|
hal_clock_put(sunxi_pwm.pwm_bus_clk);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
PWM_INFO("pwm deinit end");
|
|||
|
|
return 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
pwm_status_t hal_pwm_control(int channel, struct pwm_config *config_pwm)
|
|||
|
|
{
|
|||
|
|
PWM_INFO("pwm control start");
|
|||
|
|
|
|||
|
|
uint32_t ret;
|
|||
|
|
unsigned int temp;
|
|||
|
|
unsigned long long c = 0;
|
|||
|
|
unsigned long entire_cycles = 256, active_cycles = 192;
|
|||
|
|
unsigned int reg_offset, reg_shift, reg_width;
|
|||
|
|
unsigned int reg_bypass_shift /*, group_reg_offset*/;
|
|||
|
|
unsigned int reg_clk_src_shift, reg_clk_src_width;
|
|||
|
|
unsigned int reg_div_m_shift, reg_div_m_width, value;
|
|||
|
|
|
|||
|
|
PWM_INFO("period_ns = %ld", config_pwm->period_ns);
|
|||
|
|
PWM_INFO("duty_ns = %ld", config_pwm->duty_ns);
|
|||
|
|
PWM_INFO("polarity = %d", config_pwm->polarity);
|
|||
|
|
PWM_INFO("channel = %d", channel);
|
|||
|
|
|
|||
|
|
if ((config_pwm->period_ns < config_pwm->duty_ns) || (!config_pwm->period_ns))
|
|||
|
|
{
|
|||
|
|
PWM_ERR("paremeter error : period_ns can't greater than duty_ns and period_ns can't be 0");
|
|||
|
|
return -1;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* pwm set port */
|
|||
|
|
ret = hal_pwm_pinctrl_init(sunxi_pwm, channel);
|
|||
|
|
if (ret)
|
|||
|
|
{
|
|||
|
|
hal_gpio_pinmux_set_function(pwm_gpio[channel].pwm_pin, pwm_gpio[channel].pwm_function);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* pwm enable controller */
|
|||
|
|
hal_pwm_enable_controller(channel);
|
|||
|
|
|
|||
|
|
/* pwm set polarity */
|
|||
|
|
hal_pwm_porality(channel, config_pwm->polarity);
|
|||
|
|
|
|||
|
|
/* pwm config function */
|
|||
|
|
uint32_t pre_scal_id = 0, div_m = 0, prescale = 0;
|
|||
|
|
uint32_t pre_scal[][2] =
|
|||
|
|
{
|
|||
|
|
/*reg_val clk_pre_div*/
|
|||
|
|
{0, 1},
|
|||
|
|
{1, 2},
|
|||
|
|
{2, 4},
|
|||
|
|
{3, 8},
|
|||
|
|
{4, 16},
|
|||
|
|
{5, 32},
|
|||
|
|
{6, 64},
|
|||
|
|
{7, 128},
|
|||
|
|
{8, 256},
|
|||
|
|
};
|
|||
|
|
|
|||
|
|
reg_clk_src_shift = PWM_CLK_SRC_SHIFT;
|
|||
|
|
reg_clk_src_width = PWM_CLK_SRC_WIDTH;
|
|||
|
|
reg_offset = get_pccr_reg_offset(channel);
|
|||
|
|
|
|||
|
|
if (config_pwm->period_ns > 0 && config_pwm->period_ns <= 10)
|
|||
|
|
{
|
|||
|
|
/* if freq lt 100M, then direct output 100M clock,set by pass. */
|
|||
|
|
c = 100000000;
|
|||
|
|
reg_bypass_shift = channel;
|
|||
|
|
reg_offset = get_pccr_reg_offset(channel);
|
|||
|
|
|
|||
|
|
temp = hal_readl(PWM_BASE + PWM_PCGR);
|
|||
|
|
temp = SET_BITS(reg_bypass_shift, 1, temp, 1); /* bypass set */
|
|||
|
|
hal_writel(temp, PWM_BASE + PWM_PCGR);
|
|||
|
|
/*clk_src_reg*/
|
|||
|
|
temp = hal_readl(PWM_BASE + reg_offset);
|
|||
|
|
temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);/*clock source*/
|
|||
|
|
hal_writel(temp, PWM_BASE + reg_offset);
|
|||
|
|
|
|||
|
|
return 0;
|
|||
|
|
}
|
|||
|
|
else if (config_pwm->period_ns > 10 && config_pwm->period_ns <= 334)
|
|||
|
|
{
|
|||
|
|
/* if freq between 3M~100M, then select 100M as clock */
|
|||
|
|
c = 100000000;
|
|||
|
|
|
|||
|
|
/*clk_src_reg : use APB1 clock */
|
|||
|
|
temp = hal_readl(PWM_BASE + reg_offset);
|
|||
|
|
temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);
|
|||
|
|
hal_writel(temp, PWM_BASE + reg_offset);
|
|||
|
|
}
|
|||
|
|
else if (config_pwm->period_ns > 334)
|
|||
|
|
{
|
|||
|
|
/* if freq < 3M, then select 24M clock */
|
|||
|
|
c = 24000000;
|
|||
|
|
|
|||
|
|
/*clk_src_reg : use OSC24M clock */
|
|||
|
|
temp = hal_readl(PWM_BASE + reg_offset);
|
|||
|
|
temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 0);
|
|||
|
|
hal_writel(temp, PWM_BASE + reg_offset);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
c = c * config_pwm->period_ns;
|
|||
|
|
pwm_do_div(c, 1000000000);
|
|||
|
|
entire_cycles = (unsigned long)c;
|
|||
|
|
|
|||
|
|
for (pre_scal_id = 0; pre_scal_id < 9; pre_scal_id++)
|
|||
|
|
{
|
|||
|
|
if (entire_cycles <= 65536)
|
|||
|
|
{
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
for (prescale = 0; prescale < PRESCALE_MAX + 1; prescale++)
|
|||
|
|
{
|
|||
|
|
entire_cycles = ((unsigned long)c / pre_scal[pre_scal_id][1]) / (prescale + 1);
|
|||
|
|
if (entire_cycles <= 65536)
|
|||
|
|
{
|
|||
|
|
div_m = pre_scal[pre_scal_id][0];
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
c = (unsigned long long)entire_cycles * config_pwm->duty_ns;
|
|||
|
|
pwm_do_div(c, config_pwm->period_ns);
|
|||
|
|
active_cycles = c;
|
|||
|
|
if (entire_cycles == 0)
|
|||
|
|
{
|
|||
|
|
entire_cycles++;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* config clk div_m */
|
|||
|
|
reg_div_m_shift = PWM_DIV_M_SHIFT;
|
|||
|
|
reg_div_m_width = PWM_DIV_M_WIDTH;
|
|||
|
|
temp = hal_readl(PWM_BASE + reg_offset);
|
|||
|
|
temp = SET_BITS(reg_div_m_shift, reg_div_m_width, temp, div_m);
|
|||
|
|
hal_writel(temp, PWM_BASE + reg_offset);
|
|||
|
|
|
|||
|
|
/* config gating */
|
|||
|
|
reg_shift = channel;
|
|||
|
|
value = hal_readl(PWM_BASE + PWM_PCGR);
|
|||
|
|
value = SET_BITS(reg_shift, 1, value, 1);/* set gating */
|
|||
|
|
hal_writel(value, PWM_BASE + PWM_PCGR);
|
|||
|
|
|
|||
|
|
/* config prescal */
|
|||
|
|
reg_offset = PWM_PCR + 0x20 * channel;
|
|||
|
|
reg_shift = PWM_PRESCAL_SHIFT;
|
|||
|
|
reg_width = PWM_PRESCAL_WIDTH;
|
|||
|
|
temp = hal_readl(PWM_BASE + reg_offset);
|
|||
|
|
temp = SET_BITS(reg_shift, reg_width, temp, prescale);
|
|||
|
|
hal_writel(temp, PWM_BASE + reg_offset);
|
|||
|
|
|
|||
|
|
/* config active cycles */
|
|||
|
|
reg_offset = PWM_PPR + 0x20 * channel;
|
|||
|
|
reg_shift = PWM_ACT_CYCLES_SHIFT;
|
|||
|
|
reg_width = PWM_ACT_CYCLES_WIDTH;
|
|||
|
|
temp = hal_readl(PWM_BASE + reg_offset);
|
|||
|
|
temp = SET_BITS(reg_shift, reg_width, temp, active_cycles);
|
|||
|
|
hal_writel(temp, PWM_BASE + reg_offset);
|
|||
|
|
|
|||
|
|
/* config period cycles */
|
|||
|
|
reg_offset = PWM_PPR + 0x20 * channel;
|
|||
|
|
reg_shift = PWM_PERIOD_CYCLES_SHIFT;
|
|||
|
|
reg_width = PWM_PERIOD_CYCLES_WIDTH;
|
|||
|
|
temp = hal_readl(PWM_BASE + reg_offset);
|
|||
|
|
temp = SET_BITS(reg_shift, reg_width, temp, (entire_cycles - 1));
|
|||
|
|
hal_writel(temp, PWM_BASE + reg_offset);
|
|||
|
|
|
|||
|
|
PWM_INFO("pwm control end ");
|
|||
|
|
|
|||
|
|
return 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
pwm_status_t hal_pwm_resume(void)
|
|||
|
|
{
|
|||
|
|
if (hal_reset_control_assert(sunxi_pwm.pwm_reset))
|
|||
|
|
{
|
|||
|
|
return -1;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (hal_reset_control_deassert(sunxi_pwm.pwm_reset))
|
|||
|
|
{
|
|||
|
|
return -1;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (hal_clock_enable(sunxi_pwm.pwm_bus_clk))
|
|||
|
|
{
|
|||
|
|
return -1;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
PWM_INFO("hal pwm resume");
|
|||
|
|
return 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
pwm_status_t hal_pwm_suspend(void)
|
|||
|
|
{
|
|||
|
|
if (hal_reset_control_assert(sunxi_pwm.pwm_reset))
|
|||
|
|
{
|
|||
|
|
return -1;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
if (hal_clock_disable(sunxi_pwm.pwm_bus_clk))
|
|||
|
|
{
|
|||
|
|
return -1;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
PWM_INFO("hal pwm suspend");
|
|||
|
|
return 0;
|
|||
|
|
}
|