252 lines
8.5 KiB
C
252 lines
8.5 KiB
C
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/*
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*********************************************************************************************************
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* AR100 SYSTEM
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* AR100 Software System Develop Kits
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* clock control unit module
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*
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* (c) Copyright 2012-2016, Sunny China
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* All Rights Reserved
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*
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* File : reset.c
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* By : Sunny
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* Version : v1.0
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* Date : 2012-11-22
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* Descript: reset control of a module.
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* Update : date auther ver notes
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* 2012-11-22 16:55:22 Sunny 1.0 Create this file.
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*********************************************************************************************************
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*/
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#include "ccu_i.h"
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#include "hal_prcm.h"
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#include "aw_io.h"
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#include "aw_common.h"
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#include "errno.h"
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/*
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*********************************************************************************************************
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* SET RESET STATUS OF MODULE CLOCK
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*
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* Description: set the reset status of a specific module clock.
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*
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* Arguments : mclk : the module clock ID which we want to set reset status.
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* reset : the reset status which we want to set, the detail please
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* refer to the clock status of reset.
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*
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* Returns : OK if set module clock reset status succeeded, others if failed.
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*********************************************************************************************************
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*/
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s32 ccu_set_mclk_reset(u32 mclk, s32 reset)
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{
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switch (mclk) {
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case CCU_MOD_CLK_MSGBOX0:
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writel(((readl(CCU_MSGBOX_BGR_REG) & (~(0x1 << 16))) |
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(reset << 16)),
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CCU_MSGBOX_BGR_REG);
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break;
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case CCU_MOD_CLK_MSGBOX1:
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writel(((readl(CCU_MSGBOX_BGR_REG) & (~(0x1 << 17))) |
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(reset << 17)),
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CCU_MSGBOX_BGR_REG);
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break;
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case CCU_MOD_CLK_MSGBOXR:
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writel(((readl(CCU_R_MSGBOX_BGR_REG) & (~(0x1 << 16))) |
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(reset << 16)),
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CCU_R_MSGBOX_BGR_REG);
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break;
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case CCU_MOD_CLK_R_DMA_MCLK:
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/* this is nothing to do with it */
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return OK;
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case CCU_MOD_CLK_R_DMA:
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{
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writel(((readl(CCU_R_DMA_BGR_REG) & (~(0x1 << 16))) |
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(reset << 16)),
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CCU_R_DMA_BGR_REG);
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return OK;
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}
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case CCU_MOD_CLK_R_TWI:
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{
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ccu_reg_addr->r_twi.reset = reset;
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return OK;
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}
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case CCU_MOD_CLK_R_UART:
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{
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ccu_reg_addr->r_uart.reset = reset;
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return OK;
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}
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case CCU_MOD_CLK_R_TIMER0_1:
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{
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ccu_reg_addr->r_timer.reset = reset;
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return OK;
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}
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case CCU_MOD_CLK_R_TWD:
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{
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ccu_reg_addr->r_twd.reset = reset;
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return OK;
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}
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case CCU_MOD_CLK_R_PWM:
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{
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ccu_reg_addr->r_pwm.reset = reset;
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return OK;
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}
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case CCU_MOD_CLK_R_RTC:
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{
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ccu_reg_addr->r_owc.reset = reset;
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return OK;
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}
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case CCU_MOD_CLK_R_RSB:
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{
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ccu_reg_addr->r_rsb.reset = reset;
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return OK;
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}
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case CCU_MOD_CLK_R_CIR:
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{
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ccu_reg_addr->r_ir.reset = reset;
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return OK;
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}
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case CCU_MOD_CLK_VDD_SYS:
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{
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ccu_reg_addr->sys_pwr_rst.module_reset = reset;
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return OK;
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}
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case CCU_MOD_CLK_SPINLOCK:
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{
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writel(((readl(CCU_SPINLOCK_BGR_REG) & (~(0x1 << 16)))
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| (reset << 16)), CCU_SPINLOCK_BGR_REG);
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return OK;
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}
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case CCU_MOD_CLK_MSGBOX:
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{
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writel(((readl(CCU_MSGBOX_BGR_REG) & (~(0x1 << 16)))
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| (reset << 16)), CCU_MSGBOX_BGR_REG);
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return OK;
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}
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case CCU_MOD_CLK_R_AC_ADC:
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case CCU_MOD_CLK_R_AC_DAC:
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case CCU_MOD_CLK_R_AUDIO_CODEC:
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{
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if (reset) {
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ccu_reg_addr->r_ac_gate.reset = reset;
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ccu_reg_addr->r_ac_gate.gate = reset;
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} else {
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ccu_reg_addr->r_ac_gate.gate = reset;
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ccu_reg_addr->r_ac_gate.reset = reset;
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}
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return OK;
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}
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case CCU_MOD_CLK_R_DMIC:
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{
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if (reset) {
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ccu_reg_addr->r_dmic_gate.reset = reset;
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ccu_reg_addr->r_dmic_gate.gate = reset;
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} else {
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ccu_reg_addr->r_dmic_gate.gate = reset;
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ccu_reg_addr->r_dmic_gate.reset = reset;
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}
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return OK;
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}
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case CCU_MOD_CLK_R_I2S0:
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{
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if (reset) {
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writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 0))) |
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(reset << 0)), CCU_R_I2S_BGR_REG);
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writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 16))) |
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(reset << 16)), CCU_R_I2S_BGR_REG);
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} else {
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writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 16))) |
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(reset << 16)), CCU_R_I2S_BGR_REG);
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writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 0))) |
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(reset << 0)), CCU_R_I2S_BGR_REG);
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}
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return OK;
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}
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case CCU_MOD_CLK_R_I2S1:
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{
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if (reset) {
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writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 1))) |
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(reset << 1)), CCU_R_I2S_BGR_REG);
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writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 17))) |
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(reset << 17)), CCU_R_I2S_BGR_REG);
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} else {
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writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 17))) |
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(reset << 17)), CCU_R_I2S_BGR_REG);
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writel(((readl(CCU_R_I2S_BGR_REG) & (~(0x1 << 1))) |
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(reset << 1)), CCU_R_I2S_BGR_REG);
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}
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return OK;
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}
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case CCU_MOD_CLK_R_MAD_CFG:
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{
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if (reset) {
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 1))) |
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(reset << 1)), CCU_R_MAD_BGR_REG);
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 17))) |
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(reset << 17)), CCU_R_MAD_BGR_REG);
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} else {
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 17))) |
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(reset << 17)), CCU_R_MAD_BGR_REG);
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 1))) |
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(reset << 1)), CCU_R_MAD_BGR_REG);
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}
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return OK;
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}
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case CCU_MOD_CLK_R_MAD:
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{
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if (reset) {
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 0))) |
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(reset << 0)), CCU_R_MAD_BGR_REG);
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 16))) |
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(reset << 16)), CCU_R_MAD_BGR_REG);
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} else {
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 16))) |
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(reset << 16)), CCU_R_MAD_BGR_REG);
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 0))) |
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(reset << 0)), CCU_R_MAD_BGR_REG);
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}
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return OK;
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}
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case CCU_MOD_CLK_R_MAD_SRAM:
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{
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if (reset) {
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 3))) |
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(reset << 3)), CCU_R_MAD_BGR_REG);
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 19))) |
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(reset << 19)), CCU_R_MAD_BGR_REG);
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} else {
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 19))) |
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(reset << 19)), CCU_R_MAD_BGR_REG);
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 3))) |
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(reset << 3)), CCU_R_MAD_BGR_REG);
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}
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return OK;
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}
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case CCU_MOD_CLK_R_LPSD:
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{
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if (reset) {
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 18))) |
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(reset << 18)), CCU_R_MAD_BGR_REG);
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} else {
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writel(((readl(CCU_R_MAD_BGR_REG) & (~(0x1 << 18))) |
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(reset << 18)), CCU_R_MAD_BGR_REG);
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}
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return OK;
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}
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default:
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{
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pr_warning("invaid module clock id (%d) when set reset\n",
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mclk);
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return -EINVAL;
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}
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}
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/* un-reached */
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return OK;
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}
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s32 ccu_reset_module(u32 mclk)
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{
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/* module reset method: set as reset valid->set as reset invalid */
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ccu_set_mclk_reset(mclk, CCU_CLK_RESET);
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ccu_set_mclk_reset(mclk, CCU_CLK_NRESET);
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return OK;
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}
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