120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 huangzhenwei@allwinnertech.com
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*/
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#include "ccu.h"
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#include "ccu_common.h"
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#include "ccu_reset.h"
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#include "ccu_div.h"
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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#include "ccu_nm.h"
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#include "ccu-sun8iw20-r.h"
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static const char *const ahbs_apbs0_parents[] = { "dcxo24M", "osc32k",
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"iosc", "pll-periph0-div3"
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};
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static SUNXI_CCU_MP_WITH_MUX(r_ahb_clk, "r-ahb",
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ahbs_apbs0_parents, 0x000,
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0, 5,
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8, 2,
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24, 3,
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0);
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static SUNXI_CCU_MP_WITH_MUX(r_apb0_clk, "r-apb0",
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ahbs_apbs0_parents, 0x00c,
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0, 5,
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8, 2,
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24, 3,
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0);
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static SUNXI_CCU_GATE(r_apb0_timer_clk, "r-apb0-timer", "r-apb0",
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0x11c, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb0_twd_clk, "r-apb0-twd", "r-apb0",
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0x12c, BIT(0), 0);
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static SUNXI_CCU_GATE(r_ppu_clk, "r-ppu", "r-apb0",
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0x1ac, BIT(0), 0);
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static const char *const r_apb0_ir_rx_parents[] = { "osc32k", "dcxo24M" };
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static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb0_ir_rx_clk, "r-apb0-ir-rx",
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r_apb0_ir_rx_parents, 0x1c0,
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0, 5, /* M */
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8, 2, /* P */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_GATE(r_apb0_bus_ir_rx_clk, "r-apb0-bus-ir-rx", "r-apb0",
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0x1cc, BIT(0), 0);
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static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",
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0x20c, BIT(0), 0);
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static SUNXI_CCU_GATE(r_apb0_cpucfg_clk, "r-apb0-cpucfg", "r-apb0",
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0x22c, BIT(0), 0);
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static struct ccu_common *sun8iw20_r_ccu_clks[] =
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{
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&r_ahb_clk.common,
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&r_apb0_clk.common,
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&r_apb0_timer_clk.common,
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&r_apb0_twd_clk.common,
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&r_ppu_clk.common,
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&r_apb0_ir_rx_clk.common,
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&r_apb0_bus_ir_rx_clk.common,
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&r_ahb_bus_rtc_clk.common,
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&r_apb0_cpucfg_clk.common,
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};
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static struct clk_hw_onecell_data sun8iw20_r_hw_clks =
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{
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.hws = {
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[CLK_R_AHB] = &r_ahb_clk.common.hw,
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[CLK_R_APB0] = &r_apb0_clk.common.hw,
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[CLK_R_APB0_TIMER] = &r_apb0_timer_clk.common.hw,
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[CLK_R_APB0_TWD] = &r_apb0_twd_clk.common.hw,
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[CLK_R_PPU] = &r_ppu_clk.common.hw,
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[CLK_R_APB0_IRRX] = &r_apb0_ir_rx_clk.common.hw,
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[CLK_R_APB0_BUS_IRRX] = &r_apb0_bus_ir_rx_clk.common.hw,
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[CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw,
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[CLK_R_APB0_CPUCFG] = &r_apb0_cpucfg_clk.common.hw,
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},
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.num = CLK_R_NUMBER,
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};
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static struct ccu_reset_map sun8iw20_r_ccu_resets[] =
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{
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[RST_R_APB0_TIMER] = { 0x11c, BIT(16) },
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[RST_R_APB0_TWD] = { 0x12c, BIT(16) },
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[RST_R_PPU] = { 0x1ac, BIT(16) },
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[RST_R_APB0_BUS_IRRX] = { 0x1cc, BIT(16) },
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[RST_R_AHB_BUS_RTC] = { 0x20c, BIT(16) },
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[RST_R_APB0_CPUCFG] = { 0x22c, BIT(16) },
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};
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static const struct sunxi_ccu_desc sun8iw20_r_ccu_desc =
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{
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.ccu_clks = sun8iw20_r_ccu_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8iw20_r_ccu_clks),
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.hw_clks = &sun8iw20_r_hw_clks,
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.clk_type = HAL_SUNXI_R_CCU,
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.resets = sun8iw20_r_ccu_resets,
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.reset_type = HAL_SUNXI_R_RESET,
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.num_resets = ARRAY_SIZE(sun8iw20_r_ccu_resets),
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};
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int sunxi_r_ccu_init(void)
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{
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unsigned long reg = (unsigned long)SUNXI_R_CCU_BASE;
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return ccu_common_init(reg, &sun8iw20_r_ccu_desc);
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}
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