2015-09-06 16:37:43 +08:00
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/*
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2018-10-22 11:02:14 +08:00
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* Copyright (c) 2006-2018, RT-Thread Development Team
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2015-09-06 16:37:43 +08:00
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*
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2018-10-22 11:02:14 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-09-06 16:37:43 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2015-09-02 heyuanjie87 the first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "lpc_timer.h"
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#include "lpc_clkpwr.h"
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#include "drv_hwtimer.h"
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#ifdef RT_USING_HWTIMER
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static void NVIC_Configuration(void)
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{
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NVIC_EnableIRQ(TIMER0_IRQn);
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}
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static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state)
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{
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LPC_TIM_TypeDef *tim;
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TIM_TIMERCFG_Type cfg;
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tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
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TIM_DeInit(tim);
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if (state == 1)
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{
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NVIC_Configuration();
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cfg.PrescaleOption = TIM_PRESCALE_TICKVAL;
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cfg.PrescaleValue = 0xFFFF;
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TIM_Init(tim, TIM_TIMER_MODE, &cfg);
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}
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}
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static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
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{
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LPC_TIM_TypeDef *tim;
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TIM_MATCHCFG_Type match;
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tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
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match.MatchChannel = 0;
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match.IntOnMatch = ENABLE;
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match.ResetOnMatch = ENABLE;
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2019-03-08 15:02:46 +08:00
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match.StopOnMatch = (opmode == HWTIMER_MODE_ONESHOT) ? ENABLE : DISABLE;
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2015-09-06 16:37:43 +08:00
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match.ExtMatchOutputType = 0;
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match.MatchValue = t;
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TIM_ConfigMatch(tim, &match);
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TIM_Cmd(tim, ENABLE);
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return RT_EOK;
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}
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static void timer_stop(rt_hwtimer_t *timer)
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{
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LPC_TIM_TypeDef *tim;
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tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
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TIM_Cmd(tim, DISABLE);
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}
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static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
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{
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LPC_TIM_TypeDef *tim;
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rt_err_t err = RT_EOK;
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tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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uint32_t clk;
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uint32_t pre;
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clk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
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2019-03-08 15:02:46 +08:00
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pre = clk / *((uint32_t *)arg) - 1;
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2015-09-06 16:37:43 +08:00
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tim->PR = pre;
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}
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break;
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default:
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{
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err = -RT_ENOSYS;
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}
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break;
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}
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return err;
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}
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static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
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{
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LPC_TIM_TypeDef *tim;
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tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
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return tim->TC;
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}
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static const struct rt_hwtimer_info _info =
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{
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1000000, /* the maximum count frequency can be set */
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2000, /* the minimum count frequency can be set */
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0xFFFFFF, /* the maximum counter value */
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HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */
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};
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static const struct rt_hwtimer_ops _ops =
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{
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timer_init,
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timer_start,
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timer_stop,
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timer_counter_get,
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timer_ctrl,
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};
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static rt_hwtimer_t _timer0;
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2019-03-08 15:02:46 +08:00
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int rt_hw_hwtimer_init(void)
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2015-09-06 16:37:43 +08:00
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{
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_timer0.info = &_info;
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_timer0.ops = &_ops;
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rt_device_hwtimer_register(&_timer0, "timer0", LPC_TIM0);
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return 0;
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}
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void TIMER0_IRQHandler(void)
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{
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if (TIM_GetIntStatus(LPC_TIM0, TIM_MR0_INT) != RESET)
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{
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TIM_ClearIntPending(LPC_TIM0, TIM_MR0_INT);
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rt_device_hwtimer_isr(&_timer0);
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}
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}
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2019-03-08 15:02:46 +08:00
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INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
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#endif /* RT_USING_HWTIMER */
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