248 lines
8.5 KiB
C
248 lines
8.5 KiB
C
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/**
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*****************************************************************************
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* @file cmem7_i2c.h
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*
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* @brief CMEM7 I2C header file
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*
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*
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* @version V1.0
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* @date 3. September 2013
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*
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* @note
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*
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*****************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2>
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*****************************************************************************
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*/
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#ifndef __CMEM7_I2C_H
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#define __CMEM7_I2C_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "cmem7.h"
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#include "cmem7_conf.h"
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#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C0) || \
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((PERIPH) == I2C1))
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/** @defgroup I2C_Mode
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* @{
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*/
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#define I2C_Mode_Slave 0
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#define I2C_Mode_Master 1
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#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_Slave) || \
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((MODE) == I2C_Mode_Master))
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/**
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* @}
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*/
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/** @defgroup I2C_ADDR_WIDTH
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* @{
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*/
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#define I2C_ADDR_WIDTH_7BIT 0
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#define I2C_ADDR_WIDTH_10BIT 1
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#define IS_I2C_ADDR_WIDTH(WIDTH) (((WIDTH) == I2C_ADDR_WIDTH_7BIT) || \
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((WIDTH) == I2C_ADDR_WIDTH_10BIT))
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/**
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* @}
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*/
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/** @defgroup I2C_INT
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* @{
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*/
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#define I2C_INT_RX_FIFO_NOT_EMPTY 0x00000004 /*!< Can't be clear but read FIFO */
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#define I2C_INT_RD_REQUEST 0x00000020 /*!< Slave was requested to send data */
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#define I2C_INT_TX_ABORT 0x00000040 /*!< Error while sending data */
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#define I2C_INT_RX_DONE 0x00000080 /*!< Slave sent all requested data */
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#define I2C_INT_TX_DONE 0x00000100 /*!< Master accomplish to send all data */
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#define I2C_INT_ALL (I2C_INT_RX_FIFO_NOT_EMPTY | \
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I2C_INT_RD_REQUEST | \
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I2C_INT_TX_ABORT | \
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I2C_INT_RX_DONE | \
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I2C_INT_TX_DONE)
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#define IS_I2C_INT(INT) (((INT) != 0) && (((INT) & ~I2C_INT_ALL) == 0))
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/**
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* @}
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*/
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/** @defgroup I2C_STATUS
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* @{
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*/
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#define I2C_STATUS_RX_FIFO_NOT_EMPTY 0x00200000 /*!< Can't be clear but read FIFO */
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#define I2C_STATUS_RD_REQUEST 0x01000000 /*!< Slave was requested to send data */
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#define I2C_STATUS_TX_ABORT 0x02000000 /*!< Error while sending data */
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#define I2C_STATUS_RX_DONE 0x04000000 /*!< Slave sent all requested data */
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#define I2C_STATUS_TX_DONE 0x08000000 /*!< Master accomplish to send all data */
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#define I2C_STATUS_ALL (I2C_STATUS_RX_FIFO_NOT_EMPTY | \
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I2C_STATUS_RD_REQUEST | \
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I2C_STATUS_TX_ABORT | \
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I2C_STATUS_RX_DONE | \
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I2C_STATUS_TX_DONE)
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#define IS_I2C_STATUS(STATUS) (((STATUS) != 0) && (((STATUS) & ~I2C_STATUS_ALL) == 0))
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/**
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* @}
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*/
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/**
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* @brief I2C timing structure
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*/
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typedef struct
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{
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uint32_t I2C_Freq; /*!< I2C frquency */
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uint16_t I2C_TsuDat; /*!< nano second of TSU:DAT */
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uint16_t I2C_Tsetup; /*!< nano second of THD:STA and TSU:STO */
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uint16_t I2C_Tbuf; /*!< nano second of TBUF */
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uint16_t I2C_TsuSta; /*!< nano second of TSU:STA */
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BOOL I2C_SdaFilterEn; /*!< enabled flag of SDA filter */
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uint8_t I2C_SdaFilterSpike; /*!< spikes of SDA filter */
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BOOL I2C_SclFilterEn; /*!< enabled flag of SCL filter */
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uint8_t I2C_SclFilterSpike; /*!< spikes of SCL filter */
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} I2C_InitTimingDef;
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/**
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* @brief I2C initialization structure
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*/
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typedef struct
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{
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uint8_t I2C_Mode; /*!< Specifies the I2C mode.
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This parameter can be a value of @ref I2C_mode */
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uint8_t I2C_AddressWidth; /*!< 7- or 10-bits width address, ref as @ref I2C_ADDR_WIDTH */
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uint8_t I2C_Address; /*!< 7- or 10-bits address */
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I2C_InitTimingDef* timing; /*!< timing structure, null if don't set */
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} I2C_InitTypeDef;
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/**
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* @brief I2C initialization
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* @note This function should be called at first before any other interfaces.
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] init A pointer to structure I2C_InitTypeDef
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* @retval None
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*/
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void I2C_Init(I2C0_Type* I2Cx, I2C_InitTypeDef* I2C_Init);
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/**
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* @brief Enable or disable I2C.
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] Enable The bit indicates if the specific I2C is enable or not
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* @retval None
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*/
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void I2C_Enable(I2C0_Type* I2Cx, BOOL enable);
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/**
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* @brief Enable or disable I2C interrupt.
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
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* @param[in] Enable The bit indicates if specific interrupts are enable or not
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* @retval None
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*/
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void I2C_EnableInt(I2C0_Type* I2Cx, uint32_t Int, BOOL enable);
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/**
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* @brief Check specific interrupts are set or not
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
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* @retval BOOL The bit indicates if specific interrupts are enable or not
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*/
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BOOL I2C_GetIntStatus(I2C0_Type* I2Cx, uint32_t Int);
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/**
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* @brief Clear specific interrupts
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* @note Specific interrupt clear will clear correspective status as well
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
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* @retval None
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*/
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void I2C_ClearInt(I2C0_Type* I2Cx, uint32_t Int);
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/**
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* @brief Check specific status are set or not
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
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* @retval BOOL The bit indicates if specific status are set or not
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*/
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BOOL I2C_GetStatus(I2C0_Type* I2Cx, uint32_t Status);
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/**
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* @brief Clear specific status
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* @note Specific status clear will clear correspective interrupt as well
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
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* @retval None
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*/
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void I2C_ClearStatus(I2C0_Type* I2Cx, uint32_t Status);
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/**
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* @brief I2C send read request in master mode
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* @note Users must call I2C_StopReq between 2 requests
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] size Expected data size to be read
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* @retval BOOL The bit indicates if read request to be sent is valid
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* @see I2C_StopReq
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*/
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BOOL I2C_MasterReadReq(I2C0_Type* I2Cx, uint8_t size);
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/**
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* @brief Read data from I2C
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] size Expected data size to be read
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* @param[out] Data A user-allocated buffer to fetch data to be read
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* @retval uint8_t Actual read data size
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*/
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uint8_t I2C_ReadFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
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/**
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* @brief I2C send write request in master or slave mode
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* @note Users must call I2C_StopReq between 2 requests
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] size Expected data size to be written, includes the first data
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* @param[in] firstData The first data to be written
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* @retval BOOL The bit indicates if write request to be sent is valid
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* @see I2C_StopReq
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*/
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BOOL I2C_WriteReq(I2C0_Type* I2Cx, uint8_t size, uint8_t firstData);
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/**
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* @brief Write data to I2C
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @param[in] size Expected data size to be written
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* @param[in] Data A pointer to the data to be written
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* @retval uint8_t Actual written data size
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*/
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uint8_t I2C_WriteFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
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/**
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* @brief I2C stop request
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* @note Users must call I2C_StopReq between 2 requests
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* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
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* @retval BOOL The bit indicates if request is stopped.
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* @see I2C_MasterReadReq I2C_WriteReq
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*/
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BOOL I2C_StopReq(I2C0_Type* I2Cx);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__CMEM7_I2C_H */
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