306 lines
8.5 KiB
C
306 lines
8.5 KiB
C
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/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-4-20 FYChou First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_QEI)
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#include <rtdevice.h>
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#include "NuMicro.h"
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/* Private define ---------------------------------------------------------------*/
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/* Private typedef --------------------------------------------------------------*/
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struct nu_qei
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{
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struct rt_pulse_encoder_device dev;
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char *name;
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QEI_T *qei_base;
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rt_uint32_t max_cntval;
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rt_uint32_t cmp_val;
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IRQn_Type IRQn;
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rt_uint8_t qei_type;
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rt_uint8_t qei_flag;
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};
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typedef struct nu_qei *nu_qei_t;
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/* Private functions ------------------------------------------------------------*/
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static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder);
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static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder);
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static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder);
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static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder);
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static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args);
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/* Public functions -------------------------------------------------------------*/
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rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder);
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rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder);
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rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder);
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void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type);
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void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val);
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/* Private variables ------------------------------------------------------------*/
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static struct nu_qei nu_qei_arr [] =
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{
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#if defined(BSP_USING_QEI0)
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{
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.name = "qei0",
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.qei_base = QEI0,
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.max_cntval = 1000,
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.cmp_val = 100,
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.IRQn = QEI0_IRQn,
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.qei_type = AB_PHASE_PULSE_ENCODER,
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.qei_flag = 0
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},
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#endif
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#if defined(BSP_USING_QEI1)
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{
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.name = "qei1",
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.qei_base = QEI1,
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.max_cntval = 1000,
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.cmp_val = 100,
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.IRQn = QEI1_IRQn,
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.qei_type = AB_PHASE_PULSE_ENCODER,
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.qei_flag = 0
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},
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#endif
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{0}
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};
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static const struct rt_pulse_encoder_ops nu_qei_ops =
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{
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.init = nu_qei_init,
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.get_count = nu_qei_get_count,
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.clear_count = nu_qei_clear_count,
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.control = nu_qei_control,
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};
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typedef struct rt_pulse_encoder_ops *nu_qei_ops_t;
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/* Public variables -------------------------------------------------------------*/
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static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder)
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{
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rt_uint32_t u32type;
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switch (pulse_encoder->type)
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{
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case SINGLE_PHASE_PULSE_ENCODER:
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u32type = (((nu_qei_t)pulse_encoder)->cmp_val) ? QEI_CTL_X2_COMPARE_COUNTING_MODE : QEI_CTL_X2_FREE_COUNTING_MODE;
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break;
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case UNKNOWN_PULSE_ENCODER_TYPE:
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case AB_PHASE_PULSE_ENCODER:
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default:
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u32type = (((nu_qei_t)pulse_encoder)->cmp_val) ? QEI_CTL_X4_COMPARE_COUNTING_MODE : QEI_CTL_X4_FREE_COUNTING_MODE;
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break;
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}
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return u32type;
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}
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static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder)
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{
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rt_uint32_t u32type;
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QEI_T *qui_base;
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RT_ASSERT(pulse_encoder != RT_NULL);
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qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
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/* enable noise filter */
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QEI_ENABLE_NOISE_FILTER(qui_base, QEI_CTL_NFCLKSEL_DIV2);
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/* set qei mode */
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u32type = nu_qei_type(pulse_encoder);
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/* set compare value and interrupt */
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if (((nu_qei_t)pulse_encoder)->cmp_val)
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{
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QEI_SET_CNT_CMP(qui_base, ((nu_qei_t)pulse_encoder)->cmp_val);
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QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk);
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QEI_ENABLE_CNT_CMP(qui_base);
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NVIC_EnableIRQ(((nu_qei_t)pulse_encoder)->IRQn);
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}
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QEI_Open(qui_base, u32type, ((nu_qei_t)pulse_encoder)->max_cntval);
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return RT_EOK;
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}
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static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder)
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{
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QEI_T *qui_base;
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RT_ASSERT(pulse_encoder != RT_NULL);
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qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
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return (rt_int32_t)QEI_GET_CNT_VALUE(qui_base);
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}
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static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
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{
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QEI_T *qui_base;
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RT_ASSERT(pulse_encoder != RT_NULL);
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qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
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QEI_Stop(qui_base);
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QEI_SET_CNT_VALUE(qui_base, 0);
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QEI_Start(qui_base);
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return RT_EOK;
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}
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static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
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{
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rt_err_t result;
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QEI_T *qui_base;
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RT_ASSERT(pulse_encoder != RT_NULL);
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qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
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RT_ASSERT(cmd != RT_NULL);
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result = RT_EOK;
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switch (cmd)
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{
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case PULSE_ENCODER_CMD_ENABLE:
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QEI_Start(qui_base);
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if (((nu_qei_t)pulse_encoder)->cmp_val)
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{
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QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk);
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QEI_ENABLE_CNT_CMP(qui_base);
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NVIC_EnableIRQ(((nu_qei_t)pulse_encoder)->IRQn);
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}
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break;
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case PULSE_ENCODER_CMD_DISABLE:
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if (((nu_qei_t)pulse_encoder)->cmp_val)
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{
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QEI_DisableInt(qui_base, QEI_CTL_CMPIEN_Msk);
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QEI_DISABLE_CNT_CMP(qui_base);
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NVIC_DisableIRQ(((nu_qei_t)pulse_encoder)->IRQn);
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}
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QEI_Stop(qui_base);
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break;
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default:
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result = -RT_ENOSYS;
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break;
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}
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return result;
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}
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#if defined(BSP_USING_QEI0)
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/* QEI0 interrupt entry */
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void QEI0_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (QEI_GET_INT_FLAG(nu_qei_arr[0].qei_base, QEI_STATUS_CMPF_Msk))
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{
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nu_qei_arr[0].qei_flag = 1;
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QEI_CLR_INT_FLAG(nu_qei_arr[0].qei_base, QEI_STATUS_CMPF_Msk);
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rt_kprintf("QEI0 CMP flag rising\n") ;
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#if defined(BSP_USING_QEI1)
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/* QEI1 interrupt entry */
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void QEI1_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (QEI_GET_INT_FLAG(nu_qei_arr[1].qei_base, QEI_STATUS_CMPF_Msk))
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{
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nu_qei_arr[1].qei_flag = 1;
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QEI_CLR_INT_FLAG(nu_qei_arr[1].qei_base, QEI_STATUS_CMPF_Msk);
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rt_kprintf("QEI1 CMP flag rising\n") ;
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder)
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{
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return ((nu_qei_t) * pulse_encoder)->max_cntval;
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}
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rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder)
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{
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return ((nu_qei_t) * pulse_encoder)->cmp_val;
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}
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rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder)
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{
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return ((nu_qei_t) * pulse_encoder)->qei_type;
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}
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void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type)
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{
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QEI_T *qui_base;
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RT_ASSERT(pulse_encoder != RT_NULL);
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qui_base = ((nu_qei_t) * pulse_encoder)->qei_base;
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RT_ASSERT(u8type <= AB_PHASE_PULSE_ENCODER);
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((nu_qei_t)*pulse_encoder)->qei_type = u8type;
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((nu_qei_t)*pulse_encoder)->dev.type = (enum rt_pulse_encoder_type)u8type;
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((nu_qei_t)*pulse_encoder)->max_cntval = u32val;
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QEI_Open(qui_base, nu_qei_type(&(((nu_qei_t)*pulse_encoder)->dev)), u32val);
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}
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void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val)
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{
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QEI_T *qui_base;
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RT_ASSERT(pulse_encoder != RT_NULL);
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qui_base = ((nu_qei_t) * pulse_encoder)->qei_base;
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((nu_qei_t)*pulse_encoder)->cmp_val = u32val;
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QEI_SET_CNT_CMP(qui_base, ((nu_qei_t)*pulse_encoder)->cmp_val);
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if (((nu_qei_t)*pulse_encoder)->cmp_val)
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{
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QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk);
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QEI_ENABLE_CNT_CMP(qui_base);
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NVIC_EnableIRQ(((nu_qei_t)*pulse_encoder)->IRQn);
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}
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else
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{
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QEI_DisableInt(qui_base, QEI_CTL_CMPIEN_Msk);
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QEI_DISABLE_CNT_CMP(qui_base);
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NVIC_DisableIRQ(((nu_qei_t)*pulse_encoder)->IRQn);
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}
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}
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int rt_hw_qei_init(void)
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{
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int result = RT_ERROR;
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int nu_sel = 0;
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while (nu_qei_arr[nu_sel].name != 0)
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{
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nu_qei_arr[nu_sel].dev.type = (enum rt_pulse_encoder_type)nu_qei_arr[nu_sel].qei_type;
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nu_qei_arr[nu_sel].dev.ops = &nu_qei_ops;
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result = rt_device_pulse_encoder_register((void *)&nu_qei_arr[nu_sel], nu_qei_arr[nu_sel].name, &(nu_qei_arr[nu_sel].qei_flag));
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RT_ASSERT(result == RT_EOK);
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nu_sel++;
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}
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return result;
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}
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INIT_APP_EXPORT(rt_hw_qei_init);
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#endif /* BSP_USING_QEI */
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