394 lines
11 KiB
C
394 lines
11 KiB
C
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/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-2-05 HPHuang First version
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******************************************************************************/
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#include <rtconfig.h>
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#ifdef BSP_USING_I2C
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#include <rtdevice.h>
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#include <NuMicro.h>
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/* Private define ---------------------------------------------------------------*/
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#define LOG_TAG "drv.i2c"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME "drv.i2c"
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#define DBG_LEVEL DBG_ERROR
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#define DBG_COLOR
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#include <rtdbg.h>
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const rt_uint32_t u32I2C_MASTER_STATUS_START = 0x08UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_REPEAT_START = 0x10UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK = 0x18UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_NACK = 0x20UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_DATA_ACK = 0x28UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_DATA_NACK = 0x30UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_ARBITRATION_LOST = 0x38UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK = 0x40UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_NACK = 0x48UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_DATA_ACK = 0x50UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_DATA_NACK = 0x58UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_BUS_ERROR = 0x00UL;
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const rt_uint32_t u32I2C_MASTER_STATUS_BUS_RELEASED = 0xF8UL;
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/* Private typedef --------------------------------------------------------------*/
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typedef struct _nu_i2c_bus
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{
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struct rt_i2c_bus_device parent;
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I2C_T *I2C;
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struct rt_i2c_msg *msg;
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char *device_name;
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} nu_i2c_bus_t;
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/* Private variables ------------------------------------------------------------*/
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#ifdef BSP_USING_I2C0
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#define I2C0BUS_NAME "i2c0"
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static nu_i2c_bus_t nu_i2c0 =
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{
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.I2C = I2C0,
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.device_name = I2C0BUS_NAME,
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};
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#endif /* BSP_USING_I2C0 */
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#ifdef BSP_USING_I2C1
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#define I2C1BUS_NAME "i2c1"
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static nu_i2c_bus_t nu_i2c1 =
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{
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.I2C = I2C1,
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.device_name = I2C1BUS_NAME,
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};
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#endif /* BSP_USING_I2C1 */
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#ifdef BSP_USING_I2C2
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#define I2C2BUS_NAME "i2c2"
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static nu_i2c_bus_t nu_i2c2 =
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{
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.I2C = I2C2,
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.device_name = I2C2BUS_NAME,
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};
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#endif /* BSP_USING_I2C2 */
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/* Private functions ------------------------------------------------------------*/
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#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2))
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static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num);
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static const struct rt_i2c_bus_device_ops nu_i2c_ops =
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{
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.master_xfer = nu_i2c_mst_xfer,
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.slave_xfer = NULL,
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.i2c_bus_control = NULL,
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};
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static rt_err_t nu_i2c_configure(nu_i2c_bus_t *bus)
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{
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RT_ASSERT(bus != RT_NULL);
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bus->parent.ops = &nu_i2c_ops;
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I2C_Open(bus->I2C, 100000);
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return RT_EOK;
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}
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static inline rt_err_t nu_i2c_wait_ready_with_timeout(nu_i2c_bus_t *bus)
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{
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rt_tick_t start = rt_tick_get();
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while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk))
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{
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if ((rt_tick_get() - start) > bus->parent.timeout)
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{
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LOG_E("\ni2c: timeout!\n");
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return -RT_ETIMEOUT;
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}
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}
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return RT_EOK;
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}
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static inline rt_err_t nu_i2c_send_data(nu_i2c_bus_t *nu_i2c, rt_uint8_t data)
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{
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I2C_SET_DATA(nu_i2c->I2C, data);
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I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI);
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return nu_i2c_wait_ready_with_timeout(nu_i2c);
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}
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static rt_err_t nu_i2c_send_address(nu_i2c_bus_t *nu_i2c,
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struct rt_i2c_msg *msg)
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{
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rt_uint16_t flags = msg->flags;
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rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
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rt_uint8_t addr1, addr2;
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rt_err_t ret;
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if (flags & RT_I2C_ADDR_10BIT)
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{
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nu_i2c->I2C->CTL1 |= I2C_CTL1_ADDR10EN_Msk;
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addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
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addr2 = msg->addr & 0xff;
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LOG_D("address1: %d, address2: %d\n", addr1, addr2);
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ret = nu_i2c_send_data(nu_i2c, addr1);
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if (ret != RT_EOK) /* for timeout condition */
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return -RT_EIO;
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if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack)
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{
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LOG_E("NACK: sending first address failed\n");
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return -RT_EIO;
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}
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ret = nu_i2c_send_data(nu_i2c, addr2);
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if (ret != RT_EOK) /* for timeout condition */
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return -RT_EIO;
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if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack)
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{
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LOG_E("NACK: sending second address failed\n");
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return -RT_EIO;
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}
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if (flags & RT_I2C_RD)
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{
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LOG_D("send repeated START signal\n");
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I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI);
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ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
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if (ret != RT_EOK) /* for timeout condition */
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return -RT_EIO;
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if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_REPEAT_START) && !ignore_nack)
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{
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LOG_E("sending repeated START failed\n");
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return -RT_EIO;
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}
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addr1 |= 0x01;
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ret = nu_i2c_send_data(nu_i2c, addr1);
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if (ret != RT_EOK) /* for timeout condition */
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return -RT_EIO;
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if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK) && !ignore_nack)
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{
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LOG_E("NACK: sending read address failed\n");
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return -RT_EIO;
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}
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}
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}
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else
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{
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/* 7-bit addr */
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addr1 = msg->addr << 1;
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if (flags & RT_I2C_RD)
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addr1 |= 1;
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/* Send device address */
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ret = nu_i2c_send_data(nu_i2c, addr1); /* Send Address */
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if (ret != RT_EOK) /* for timeout condition */
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return -RT_EIO;
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if ( (I2C_GET_STATUS(nu_i2c->I2C)
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!= ((flags & RT_I2C_RD) ? u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK : u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK))
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&& !ignore_nack)
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{
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LOG_E("sending address failed\n");
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return -RT_EIO;
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}
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}
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return RT_EOK;
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}
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static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num)
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{
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struct rt_i2c_msg *msg;
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nu_i2c_bus_t *nu_i2c;
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rt_size_t i;
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rt_uint32_t cnt_data;
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rt_uint16_t ignore_nack;
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rt_err_t ret;
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RT_ASSERT(bus != RT_NULL);
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nu_i2c = (nu_i2c_bus_t *) bus;
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nu_i2c->msg = msgs;
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nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk;
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ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
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if (ret != RT_EOK) /* for timeout condition */
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{
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rt_set_errno(-RT_ETIMEOUT);
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return 0;
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}
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if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_START)
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{
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i = 0;
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LOG_E("Send START Failed");
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return i;
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}
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for (i = 0; i < num; i++)
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{
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msg = &msgs[i];
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ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
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if (!(msg->flags & RT_I2C_NO_START))
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{
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if (i)
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{
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I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI);
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ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
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if (ret != RT_EOK) /* for timeout conditrion */
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break;
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if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_REPEAT_START)
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{
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i = 0;
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LOG_E("Send repeat START Fail");
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break;
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}
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}
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if ((RT_EOK != nu_i2c_send_address(nu_i2c, msg))
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&& !ignore_nack)
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{
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i = 0;
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LOG_E("Send Address Fail");
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break;
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}
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}
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if (nu_i2c->msg[i].flags & RT_I2C_RD) /* Receive Bytes */
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{
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rt_uint32_t do_rd_nack = (i == (num - 1));
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for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++)
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{
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do_rd_nack += (cnt_data == (nu_i2c->msg[i].len - 1)); /* NACK after last byte for hardware setting */
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if (do_rd_nack == 2)
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{
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I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI);
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}
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else
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{
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I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI_AA);
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}
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ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
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if (ret != RT_EOK) /* for timeout condition */
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break;
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if (nu_i2c->I2C->CTL0 & I2C_CTL_AA)
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{
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if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_DATA_ACK)
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{
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i = 0;
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break;
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}
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}
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else
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{
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if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_DATA_NACK)
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{
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i = 0;
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break;
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}
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}
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nu_i2c->msg[i].buf[cnt_data] = nu_i2c->I2C->DAT;
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}
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}
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else /* Send Bytes */
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{
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for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++)
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{
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/* Send register number and MSB of data */
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ret = nu_i2c_send_data(nu_i2c, (uint8_t)(nu_i2c->msg[i].buf[cnt_data]));
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if (ret != RT_EOK) /* for timeout condition */
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break;
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if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_DATA_ACK
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&& !ignore_nack
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) /* Send aata and get Ack */
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{
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i = 0;
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break;
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}
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}
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}
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}
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I2C_STOP(nu_i2c->I2C);
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RT_ASSERT(I2C_GET_STATUS(nu_i2c->I2C) == u32I2C_MASTER_STATUS_BUS_RELEASED);
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if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_BUS_RELEASED)
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{
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i = 0;
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}
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nu_i2c->msg = RT_NULL;
|
||
|
|
nu_i2c->I2C->CTL1 = 0; /*clear all sub modes like 10 bit mode*/
|
||
|
|
return i;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Public functions -------------------------------------------------------------*/
|
||
|
|
int rt_hw_i2c_init(void)
|
||
|
|
{
|
||
|
|
rt_err_t ret = RT_ERROR;
|
||
|
|
#if defined(BSP_USING_I2C0)
|
||
|
|
SYS_UnlockReg();
|
||
|
|
/* Enable I2C0 clock */
|
||
|
|
SYS_ResetModule(I2C0_RST);
|
||
|
|
SYS_LockReg();
|
||
|
|
nu_i2c_configure(&nu_i2c0);
|
||
|
|
ret = rt_i2c_bus_device_register(&nu_i2c0.parent, nu_i2c0.device_name);
|
||
|
|
RT_ASSERT(RT_EOK == ret);
|
||
|
|
#endif /* BSP_USING_I2C0 */
|
||
|
|
|
||
|
|
#if defined(BSP_USING_I2C1)
|
||
|
|
SYS_UnlockReg();
|
||
|
|
/* Enable I2C1 clock */
|
||
|
|
SYS_ResetModule(I2C1_RST);
|
||
|
|
SYS_LockReg();
|
||
|
|
nu_i2c_configure(&nu_i2c1);
|
||
|
|
ret = rt_i2c_bus_device_register(&nu_i2c1.parent, nu_i2c1.device_name);
|
||
|
|
RT_ASSERT(RT_EOK == ret);
|
||
|
|
#endif /* BSP_USING_I2C1 */
|
||
|
|
|
||
|
|
#if defined(BSP_USING_I2C2)
|
||
|
|
SYS_UnlockReg();
|
||
|
|
/* Enable I2C2 clock */
|
||
|
|
SYS_ResetModule(I2C2_RST);
|
||
|
|
SYS_LockReg();
|
||
|
|
nu_i2c_configure(&nu_i2c2);
|
||
|
|
ret = rt_i2c_bus_device_register(&nu_i2c2.parent, nu_i2c2.device_name);
|
||
|
|
RT_ASSERT(RT_EOK == ret);
|
||
|
|
#endif /* BSP_USING_I2C2 */
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_i2c_init);
|
||
|
|
|
||
|
|
#endif /* BSP_USING_I2C */
|
||
|
|
|