407 lines
10 KiB
C
407 lines
10 KiB
C
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/*
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* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-06-21 CDT first version
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*/
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#include <rtdevice.h>
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#include "drv_config.h"
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// #define DRV_DEBUG
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#define LOG_TAG "drv.hwtimer"
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#include <drv_log.h>
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#ifdef BSP_USING_HWTIMER
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#include "drv_irq.h"
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enum
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{
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#ifdef BSP_USING_TMRA_1
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TMRA_1_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_2
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TMRA_2_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_3
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TMRA_3_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_4
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TMRA_4_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_5
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TMRA_5_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_6
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TMRA_6_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_7
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TMRA_7_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_8
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TMRA_8_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_9
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TMRA_9_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_10
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TMRA_10_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_11
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TMRA_11_INDEX,
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#endif
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#ifdef BSP_USING_TMRA_12
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TMRA_12_INDEX,
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#endif
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};
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struct hc32_hwtimer
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{
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rt_hwtimer_t time_device;
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CM_TMRA_TypeDef *tmr_handle;
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rt_uint32_t clock_source;
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rt_uint32_t clock;
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rt_uint32_t flag;
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struct
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{
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en_int_src_t enIntSrc;
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IRQn_Type enIRQn;
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rt_uint8_t u8Int_Prio;
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func_ptr_t irq_callback;
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} isr;
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char *name;
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};
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static struct hc32_hwtimer hc32_hwtimer_obj[] =
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{
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#ifdef BSP_USING_TMRA_1
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TMRA_1_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_2
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TMRA_2_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_3
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TMRA_3_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_4
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TMRA_4_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_5
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TMRA_5_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_6
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TMRA_6_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_7
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TMRA_7_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_8
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TMRA_8_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_9
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TMRA_9_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_10
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TMRA_10_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_11
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TMRA_11_CONFIG,
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#endif
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#ifdef BSP_USING_TMRA_12
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TMRA_12_CONFIG,
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#endif
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};
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static void _timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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stc_tmra_init_t stcTmraInit;
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struct hc32_irq_config irq_config;
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struct hc32_hwtimer *tmr_device = (struct hc32_hwtimer *)timer;
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RT_ASSERT(timer != RT_NULL);
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/* Interrupt configuration */
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irq_config.irq_num = tmr_device->isr.enIRQn;
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irq_config.int_src = tmr_device->isr.enIntSrc;
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irq_config.irq_prio = tmr_device->isr.u8Int_Prio;
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if (state) /* open */
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{
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/* Counter Frequency Fixed at maxfreq */
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timer->freq = timer->info->maxfreq;
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/* Enable TIMERA clock */
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FCG_Fcg2PeriphClockCmd(tmr_device->clock, ENABLE);
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/* TIMERA configuration */
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(void)TMRA_StructInit(&stcTmraInit);
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stcTmraInit.sw_count.u8ClockDiv = TMRA_CLK_DIV32;
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stcTmraInit.u32PeriodValue = timer->info->maxcnt;
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(void)TMRA_Init(tmr_device->tmr_handle, &stcTmraInit);
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TMRA_IntCmd(tmr_device->tmr_handle, TMRA_INT_OVF, ENABLE);
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hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_TRUE);
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}
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else /* close */
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{
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TMRA_DeInit(tmr_device->tmr_handle);
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hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_FALSE);
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FCG_Fcg2PeriphClockCmd(tmr_device->clock, DISABLE);
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}
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}
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static rt_err_t _timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
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{
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rt_err_t result = RT_EOK;
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struct hc32_hwtimer *tmr_device = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tmr_device = (struct hc32_hwtimer *)timer;
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/* set timer arr */
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TMRA_SetPeriodValue(tmr_device->tmr_handle, t - 1U);
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/* start timer */
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TMRA_Start(tmr_device->tmr_handle);
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return result;
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}
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static void _timer_stop(rt_hwtimer_t *timer)
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{
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struct hc32_hwtimer *tmr_device = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tmr_device = (struct hc32_hwtimer *)timer;
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/* stop timer */
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TMRA_Stop(tmr_device->tmr_handle);
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/* reset timer cnt */
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TMRA_SetCountValue(tmr_device->tmr_handle, 0U);
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}
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static rt_err_t _timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
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{
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rt_err_t result = -RT_ERROR;
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uint32_t freq = *(uint32_t *)arg;
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RT_ASSERT(timer != RT_NULL);
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RT_ASSERT(arg != RT_NULL);
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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if (freq != timer->freq)
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{
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LOG_W("Not Support To Set The Counter Frequency! Default is %d Hz", timer->freq);
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result = -RT_EINVAL;
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}
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else
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{
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result = RT_EOK;
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}
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}
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break;
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default:
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{
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result = -RT_EINVAL;
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}
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break;
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}
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return result;
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}
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static rt_uint32_t _timer_counter_get(rt_hwtimer_t *timer)
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{
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struct hc32_hwtimer *tmr_device = RT_NULL;
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rt_uint32_t Counter;
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RT_ASSERT(timer != RT_NULL);
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tmr_device = (struct hc32_hwtimer *)timer;
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Counter = TMRA_GetCountValue(tmr_device->tmr_handle);
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return Counter;
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}
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#ifdef BSP_USING_TMRA_1
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static void TMRA_1_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_1_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_1_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_1_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_2
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static void TMRA_2_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_2_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_2_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_2_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_3
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static void TMRA_3_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_3_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_3_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_3_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_4
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static void TMRA_4_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_4_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_4_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_4_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_5
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static void TMRA_5_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_5_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_5_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_5_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_6
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static void TMRA_6_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_6_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_6_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_6_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_7
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static void TMRA_7_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_7_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_7_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_7_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_8
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static void TMRA_8_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_8_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_8_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_8_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_9
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static void TMRA_9_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_9_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_9_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_9_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_10
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static void TMRA_10_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_10_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_10_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_10_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_11
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static void TMRA_11_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_11_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_11_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_11_INDEX].time_device);
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}
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#endif
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#ifdef BSP_USING_TMRA_12
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static void TMRA_12_callback(void)
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{
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TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_12_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_12_INDEX].flag);
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rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_12_INDEX].time_device);
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}
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#endif
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static struct rt_hwtimer_info _info[sizeof(hc32_hwtimer_obj) / sizeof(hc32_hwtimer_obj[0])];
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void tmra_get_info_callback(void)
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{
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/* Div = 32 */
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for (rt_uint8_t i = 0; i < sizeof(_info) / sizeof(_info[0]); i++)
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{
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_info[i].maxcnt = CLK_GetBusClockFreq(hc32_hwtimer_obj[i].clock_source) / 32U / 1000U; /* Period = 1ms */
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_info[i].maxfreq = CLK_GetBusClockFreq(hc32_hwtimer_obj[i].clock_source) / 32U;
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_info[i].minfreq = CLK_GetBusClockFreq(hc32_hwtimer_obj[i].clock_source) / 32U / _info[i].maxcnt;
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_info[i].cntmode = HWTIMER_CNTMODE_UP;
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}
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#ifdef BSP_USING_TMRA_1
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hc32_hwtimer_obj[TMRA_1_INDEX].isr.irq_callback = TMRA_1_callback;
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#endif
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#ifdef BSP_USING_TMRA_2
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hc32_hwtimer_obj[TMRA_2_INDEX].isr.irq_callback = TMRA_2_callback;
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#endif
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#ifdef BSP_USING_TMRA_3
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hc32_hwtimer_obj[TMRA_3_INDEX].isr.irq_callback = TMRA_3_callback;
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#endif
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#ifdef BSP_USING_TMRA_4
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hc32_hwtimer_obj[TMRA_4_INDEX].isr.irq_callback = TMRA_4_callback;
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#endif
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#ifdef BSP_USING_TMRA_5
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hc32_hwtimer_obj[TMRA_5_INDEX].isr.irq_callback = TMRA_5_callback;
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#endif
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#ifdef BSP_USING_TMRA_6
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hc32_hwtimer_obj[TMRA_6_INDEX].isr.irq_callback = TMRA_6_callback;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TMRA_7
|
||
|
|
hc32_hwtimer_obj[TMRA_7_INDEX].isr.irq_callback = TMRA_7_callback;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TMRA_8
|
||
|
|
hc32_hwtimer_obj[TMRA_8_INDEX].isr.irq_callback = TMRA_8_callback;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TMRA_9
|
||
|
|
hc32_hwtimer_obj[TMRA_9_INDEX].isr.irq_callback = TMRA_9_callback;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TMRA_10
|
||
|
|
hc32_hwtimer_obj[TMRA_10_INDEX].isr.irq_callback = TMRA_10_callback;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TMRA_11
|
||
|
|
hc32_hwtimer_obj[TMRA_11_INDEX].isr.irq_callback = TMRA_11_callback;
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TMRA_12
|
||
|
|
hc32_hwtimer_obj[TMRA_12_INDEX].isr.irq_callback = TMRA_12_callback;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_hwtimer_ops _ops =
|
||
|
|
{
|
||
|
|
.init = _timer_init,
|
||
|
|
.start = _timer_start,
|
||
|
|
.stop = _timer_stop,
|
||
|
|
.count_get = _timer_counter_get,
|
||
|
|
.control = _timer_ctrl,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int rt_hw_hwtimer_init(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
int result = RT_EOK;
|
||
|
|
|
||
|
|
tmra_get_info_callback();
|
||
|
|
for (i = 0; i < sizeof(hc32_hwtimer_obj) / sizeof(hc32_hwtimer_obj[0]); i++)
|
||
|
|
{
|
||
|
|
hc32_hwtimer_obj[i].time_device.info = &_info[i];
|
||
|
|
hc32_hwtimer_obj[i].time_device.ops = &_ops;
|
||
|
|
if (rt_device_hwtimer_register(&hc32_hwtimer_obj[i].time_device,
|
||
|
|
hc32_hwtimer_obj[i].name, &hc32_hwtimer_obj[i].tmr_handle) == RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_D("%s register success", hc32_hwtimer_obj[i].name);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_E("%s register failed", hc32_hwtimer_obj[i].name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
|
||
|
|
|
||
|
|
#endif /* BSP_USING_HWTIMER */
|