195 lines
16 KiB
C
195 lines
16 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file reg_fsmc.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
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/// MM32 FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __REG_FSMC_H
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#define __REG_FSMC_H
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// Files includes
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#include <stdint.h>
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#include <stdbool.h>
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#include "types.h"
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH Base Address Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FSMC_BANK1_ADDR (0x60000000UL )
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#define FSMC_BANK2_ADDR (0x60000000UL + 0x4000000 )
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#define FSMC_BANK3_ADDR (0x60000000UL + 0x8000000 )
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#define FSMC_BANK4_ADDR (0x60000000UL + 0xc000000 )
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#define FSMC_BASE (0x60000000UL + 0x40000000) ///< Base Address: 0xA0000000
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FSMC Registers Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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__IO u32 Reservedoffset0x00; ///< Reserved Register offset: 0x00
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__IO u32 Reservedoffset0x04; ///< Reserved Register offset: 0x04
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__IO u32 Reservedoffset0x08; ///< Reserved Register offset: 0x08
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__IO u32 Reservedoffset0x0c; ///< Reserved Register offset: 0x0c
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__IO u32 Reservedoffset0x10; ///< Reserved Register offset: 0x10
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__IO u32 Reservedoffset0x14; ///< Reserved Register offset: 0x14
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__IO u32 Reservedoffset0x18; ///< Reserved Register offset: 0x18
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__IO u32 Reservedoffset0x1c; ///< Reserved Register offset: 0x1c
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__IO u32 Reservedoffset0x20; ///< Reserved Register offset: 0x20
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__IO u32 Reservedoffset0x24; ///< Reserved Register offset: 0x24
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__IO u32 Reservedoffset0x28; ///< Reserved Register offset: 0x28
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__IO u32 Reservedoffset0x2c; ///< Reserved Register offset: 0x2c
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__IO u32 Reservedoffset0x30; ///< Reserved Register offset: 0x30
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__IO u32 Reservedoffset0x34; ///< Reserved Register offset: 0x34
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__IO u32 Reservedoffset0x38; ///< Reserved Register offset: 0x38
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__IO u32 Reservedoffset0x3c; ///< Reserved Register offset: 0x3c
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__IO u32 Reservedoffset0x40; ///< Reserved Register offset: 0x40
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__IO u32 Reservedoffset0x44; ///< Reserved Register offset: 0x44
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__IO u32 Reservedoffset0x48; ///< Reserved Register offset: 0x48
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__IO u32 Reservedoffset0x4c; ///< Reserved Register offset: 0x4c
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__IO u32 Reservedoffset0x50; ///< Reserved Register offset: 0x50
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__IO u32 SMSKR; ///< SMSKR control Register offset: 0x54
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__IO u32 Reservedoffset0x58; ///< Reserved Register offset: 0x58
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__IO u32 Reservedoffset0x5c; ///< Reserved Register offset: 0x5c
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__IO u32 Reservedoffset0x60; ///< Reserved Register offset: 0x60
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__IO u32 Reservedoffset0x64; ///< Reserved Register offset: 0x64
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__IO u32 Reservedoffset0x68; ///< Reserved Register offset: 0x68
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__IO u32 Reservedoffset0x6c; ///< Reserved Register offset: 0x6c
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__IO u32 Reservedoffset0x70; ///< Reserved Register offset: 0x70
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__IO u32 Reservedoffset0x74; ///< Reserved Register offset: 0x74
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__IO u32 Reservedoffset0x78; ///< Reserved Register offset: 0x78
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__IO u32 Reservedoffset0x7c; ///< Reserved Register offset: 0x7c
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__IO u32 Reservedoffset0x80; ///< Reserved Register offset: 0x80
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__IO u32 Reservedoffset0x84; ///< Reserved Register offset: 0x84
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__IO u32 Reservedoffset0x88; ///< Reserved Register offset: 0x88
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__IO u32 Reservedoffset0x8c; ///< Reserved Register offset: 0x8c
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__IO u32 Reservedoffset0x90; ///< Reserved Register offset: 0x90
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__IO u32 SMTMGR_SET0; ///< SMTMGR_SET Register 0 offset: 0x94
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__IO u32 SMTMGR_SET1; ///< SMTMGR_SET Register 1 offset: 0x98
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__IO u32 SMTMGR_SET2; ///< SMTMGR_SET Register 2 offset: 0x9c
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__IO u32 Reservedoffset0xA0; ///< Reserved Register offset: 0xa0
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__IO u32 SMCTLR; ///< Reserved Register offset: 0xa4
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__IO u32 Reservedoffset0xA8; ///< Reserved Register offset: 0xa8
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__IO u32 Reservedoffset0xAC; ///< Reserved Register offset: 0xac
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} FSMC_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FSMC type pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FSMC ((FSMC_TypeDef*) FSMC_BASE)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FSMC_SMSKR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FSMC_SMSKR_REG_SELECT_Pos (8)
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#define FSMC_SMSKR_REG_SELECT0 (0x00U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 0
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#define FSMC_SMSKR_REG_SELECT1 (0x01U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 1
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#define FSMC_SMSKR_REG_SELECT2 (0x02U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 2
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#define FSMC_SMSKR_MEM_TYPE_Pos (5)
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#define FSMC_SMSKR_MEM_TYPE0 (0x00U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SDRAM
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#define FSMC_SMSKR_MEM_TYPE1 (0x01U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SRAM
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#define FSMC_SMSKR_MEM_TYPE2 (0x02U << FSMC_SMSKR_MEM_TYPE_Pos) ///< FLASH
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#define FSMC_SMSKR_MEM_SIZE_Pos (0)
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#define FSMC_SMSKR_MEM_SIZE_64K (0x01U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64KB
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#define FSMC_SMSKR_MEM_SIZE_128K (0x02U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128KB
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#define FSMC_SMSKR_MEM_SIZE_256K (0x03U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256KB
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#define FSMC_SMSKR_MEM_SIZE_512K (0x04U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512KB
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#define FSMC_SMSKR_MEM_SIZE_1M (0x05U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1MB
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#define FSMC_SMSKR_MEM_SIZE_2M (0x06U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2MB
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#define FSMC_SMSKR_MEM_SIZE_4M (0x07U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4MB
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#define FSMC_SMSKR_MEM_SIZE_8M (0x08U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 8MB
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#define FSMC_SMSKR_MEM_SIZE_16M (0x09U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 16MB
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#define FSMC_SMSKR_MEM_SIZE_32M (0x10U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 32MB
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#define FSMC_SMSKR_MEM_SIZE_64M (0x11U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64MB
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#define FSMC_SMSKR_MEM_SIZE_128M (0x12U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128MB
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#define FSMC_SMSKR_MEM_SIZE_256M (0x13U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256MB
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#define FSMC_SMSKR_MEM_SIZE_512M (0x14U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512MB
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#define FSMC_SMSKR_MEM_SIZE_1G (0x15U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1GB
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#define FSMC_SMSKR_MEM_SIZE_2G (0x16U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2GB
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#define FSMC_SMSKR_MEM_SIZE_4G (0x17U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4GB
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FSMC_SMTMGR_SET0/1/2 Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FSMC_SMTMGR_SET_SM_READ_PIPE_Pos (28)
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#define FSMC_SMTMGR_SET_SM_READ_PIPE (0x03U << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) ///< The period of the latched read data
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#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos (27)
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#define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE (0x01U << FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos) ///< Access low frequency synchronization devices
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#define FSMC_SMTMGR_SET_READ_MODE_Pos (26)
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#define FSMC_SMTMGR_SET_READ_MODE (0x01U << FSMC_SMTMGR_SET_READ_MODE_Pos) ///< The Hready_RESP signal is from an external DEVICE
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#define FSMC_SMTMGR_SET_T_WP_Pos (10)
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#define FSMC_SMTMGR_SET_T_WP (0x3FU << FSMC_SMTMGR_SET_T_WP_Pos) ///< Write pulse width 64 clock cycles
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#define FSMC_SMTMGR_SET_T_WR_Pos (8)
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#define FSMC_SMTMGR_SET_T_WR (0x03U << FSMC_SMTMGR_SET_T_WR_Pos) ///< Address/data retention time for write operations is 3 clock cycles
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#define FSMC_SMTMGR_SET_T_AS_Pos (6)
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#define FSMC_SMTMGR_SET_T_AS (0x03U << FSMC_SMTMGR_SET_T_AS_Pos) ///< The address establishment time of write operation is 3 clock cycles
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#define FSMC_SMTMGR_SET_T_RC_Pos (0)
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#define FSMC_SMTMGR_SET_T_RC (0x3FU << FSMC_SMTMGR_SET_T_RC_Pos) ///< Read operation cycle 64 clock cycles
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FSMC_SMCTLR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos (13)
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos)
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 16 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 32 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 64 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 128 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 8 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos (10)
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos)
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 16 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 32 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 64 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 128 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 8 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos (7)
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos)
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 16 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 32 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 64 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 128 bits
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#define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 8 bits
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif //__REG_FSMC_H
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////////////////////////////////////////////////////////////////////////////////
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