2013-01-08 22:40:58 +08:00
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/*
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2021-04-09 10:52:34 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2013-01-08 22:40:58 +08:00
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*
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2021-04-09 10:52:34 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2013-01-08 22:40:58 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2012-02-13 mojingxian first version
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#define CLKIN 33333000LL
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#define SPEED_MULTIPLE 16
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#define BUS_DIVISOR 4
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#define CCLKSPEED (CLKIN * SPEED_MULTIPLE)
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#define SCLKSPEED (CLKIN * BUS_DIVISOR)
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#define CLOCKS_PER_SECD CCLKSPEED
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#define SCLOCKS_PER_SEC SCLKSPEED
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2021-04-09 10:52:34 +08:00
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//SIC_IMASK寄存器
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2013-01-08 22:40:58 +08:00
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#define PLL_WAKEUP_INT_MASK 0x00000001
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#define DMA_ERROR_INT_MASK 0x00000002
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#define PPI_ERROR_INT_MASK 0x00000004
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#define SPORT0_ERROR_INT_MASK 0x00000008
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#define SPORT1_ERROR_INT_MASK 0x00000010
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#define SPI_ERROR_INT_MASK 0x00000020
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#define UART_ERROR_INT_MASK 0x00000040
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#define RTC_INT_MASK 0x00000080
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#define DMA0_PPI_INT_MASK 0x00000100
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#define DMA1_SPORT0_RX_INT_MASK 0x00000200
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#define DMA2_SPORT0_TX_INT_MASK 0x00000400
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#define DMA3_SPORT1_RX_INT_MASK 0x00000800
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#define DMA4_SPORT1_TX_INT_MASK 0x00001000
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#define DMA5_SPI_INT_MASK 0x00002000
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#define DMA6_UART_RX_INT_MASK 0x00004000
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#define DMA7_UART_TX_INT_MASK 0x00008000
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#define TIMER0_INT_MASK 0x00010000
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#define TIMER1_INT_MASK 0x00020000
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#define TIMER2_INT_MASK 0x00040000
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#define PF_INTA_MASK 0x00080000
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#define PF_INTB_MASK 0x00100000
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#define MEM_DMA_STREAM0_MASK 0x00200000
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#define MEM_DMA_STREAM1_MASK 0x00400000
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#define SOFT_WATCHDOG_TMER_MASK 0x00800000
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//SIC_IAR0
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#define IAR0_PLL_WAKEUP_INT_IVG 0x00
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#define IAR0_DMA_ERROR_INT_IVG 0x01
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#define IAR0_PPI_ERROR_INT_IVG 0x02
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#define IAR0_SPORT0_ERROR_INT_IVG 0x03
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#define IAR0_SPORT1_ERROR_INT_IVG 0x04
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#define IAR0_SPI_ERROR_INT_IVG 0x05
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#define IAR0_UART_ERROR_INT_IVG 0x06
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#define IAR0_RTC_INT_IVG 0x07
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//SIC_IAR1
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#define IAR1_DMA0_PPI_INT_IVG 0x00
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#define IAR1_DMA1_SPORT0RX_IVG 0x01
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#define IAR1_DMA2_SPORT0TX_IVG 0x02
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#define IAR1_DMA3_SPORT1RX_IVG 0x03
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#define IAR1_DMA4_SPORT1TX_IVG 0x04
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#define IAR1_DMA5_SPI_INT_IVG 0x05
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#define IAR1_DMA6_UARTRX_IVG 0x06
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#define IAR1_DMA7_UARTTX_IVG 0x07
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//SIC_IAR2
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#define IAR2_TIMER0_INT_IVG 0x00
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#define IAR2_TIMER1_INT_IVG 0x01
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#define IAR2_TIMER2_INT_IVG 0x02
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#define IAR2_PF_A_INT_IVG 0x03
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#define IAR2_PF_B_INT_IVG 0x04
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#define IAR2_MEM_DMA_STREAM0_INT_IVG 0x05
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#define IAR2_MEM_DMA_STREAM1_INT_IVG 0x06
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#define IAR2_SWATCHDOG_TIMER_INT_IVG 0x07
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#ifdef __cplusplus
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extern "C" {
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#endif
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void rt_hw_core_timer_init(void);
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void rt_hw_board_init(void);
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void rt_hw_isr_install(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _BSP_H_ */
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