415 lines
13 KiB
C
415 lines
13 KiB
C
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_mu.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.mu"
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to mu clocks for each instance. */
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static const clock_ip_name_t s_muClocks[] = MU_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*! @brief Pointers to mu bases for each instance. */
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static MU_Type *const s_muBases[] = MU_BASE_PTRS;
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/******************************************************************************
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* Code
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*****************************************************************************/
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static uint32_t MU_GetInstance(MU_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0U; instance < (sizeof(s_muBases) / sizeof(s_muBases[0])); instance++)
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{
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if (s_muBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < (sizeof(s_muBases) / sizeof(s_muBases[0])));
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return instance;
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}
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/*!
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* brief Initializes the MU module.
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*
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* This function enables the MU clock only.
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*
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* param base MU peripheral base address.
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*/
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void MU_Init(MU_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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(void)CLOCK_EnableClock(s_muClocks[MU_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief De-initializes the MU module.
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*
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* This function disables the MU clock only.
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*
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* param base MU peripheral base address.
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*/
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void MU_Deinit(MU_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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(void)CLOCK_DisableClock(s_muClocks[MU_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Blocks to send a message.
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*
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* This function waits until the TX register is empty and sends the message.
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*
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* param base MU peripheral base address.
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* param regIndex TX register index.
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* param msg Message to send.
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*/
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void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg)
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{
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assert(regIndex < MU_TR_COUNT);
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/* Wait TX register to be empty. */
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while (0U == (base->SR & (((uint32_t)kMU_Tx0EmptyFlag) >> regIndex)))
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{
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; /* Intentional empty while*/
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}
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base->TR[regIndex] = msg;
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}
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/*!
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* brief Blocks to receive a message.
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*
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* This function waits until the RX register is full and receives the message.
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*
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* param base MU peripheral base address.
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* param regIndex RX register index.
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* return The received message.
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*/
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uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex)
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{
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assert(regIndex < MU_TR_COUNT);
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/* Wait RX register to be full. */
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while (0U == (base->SR & (((uint32_t)kMU_Rx0FullFlag) >> regIndex)))
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{
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; /* Intentional empty while*/
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}
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return base->RR[regIndex];
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}
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/*!
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* brief Blocks setting the 3-bit MU flags reflect on the other MU side.
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*
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* This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed,
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* the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are
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* updating to the other side. After the 3-bit MU flags are updated, the status flag
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* \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period,
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* the flags cannot be changed. This function waits for the MU status flag
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* \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags.
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*
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* param base MU peripheral base address.
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* param flags The 3-bit MU flags to set.
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*/
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void MU_SetFlags(MU_Type *base, uint32_t flags)
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{
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/* Wait for update finished. */
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while (0U != (base->SR & ((uint32_t)MU_SR_FUP_MASK)))
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{
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; /* Intentional empty while*/
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}
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MU_SetFlagsNonBlocking(base, flags);
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}
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/*!
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* brief Triggers interrupts to the other core.
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*
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* This function triggers the specific interrupts to the other core. The interrupts
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* to trigger are passed in as bit mask. See \ref _mu_interrupt_trigger.
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* The MU should not trigger an interrupt to the other core when the previous interrupt
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* has not been processed by the other core. This function checks whether the
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* previous interrupts have been processed. If not, it returns an error.
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*
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* code
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* if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger))
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* {
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* Previous general purpose interrupt 0 or general purpose interrupt 2
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* has not been processed by the other core.
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* }
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* endcode
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*
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* param base MU peripheral base address.
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* param mask Bit mask of the interrupts to trigger. See _mu_interrupt_trigger.
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* retval kStatus_Success Interrupts have been triggered successfully.
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* retval kStatus_Fail Previous interrupts have not been accepted.
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*/
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status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask)
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{
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status_t status = kStatus_Success;
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uint32_t reg = base->CR;
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/* Previous interrupt has been accepted. */
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if (0U == (reg & mask))
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{
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/* All interrupts have been accepted, trigger now. */
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reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask;
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base->CR = reg;
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status = kStatus_Success;
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}
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else
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{
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status = kStatus_Fail;
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}
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return status;
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}
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#if !(defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH)
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/*!
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* brief Boots the core at B side.
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*
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* This function sets the B side core's boot configuration and releases the
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* core from reset.
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*
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* param base MU peripheral base address.
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* param mode Core B boot mode.
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* note Only MU side A can use this function.
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*/
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void MU_BootCoreB(MU_Type *base, mu_core_boot_mode_t mode)
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{
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#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
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/* Clean the reset de-assert pending flag. */
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base->SR = MU_SR_RDIP_MASK;
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#endif
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#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR)
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uint32_t reg = base->CCR;
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reg = (reg & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK)) | MU_CCR_BOOT(mode);
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base->CCR = reg;
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#else
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uint32_t reg = base->CR;
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reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_HR_MASK | MU_CR_RSTH_MASK | MU_CR_BBOOT_MASK)) |
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MU_CR_BBOOT(mode);
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base->CR = reg;
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#endif
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}
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/*!
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* brief Boots the other core.
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*
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* This function boots the other core with a boot configuration.
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*
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* param base MU peripheral base address.
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* param mode The other core boot mode.
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*/
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void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode)
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{
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/*
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* MU_BootOtherCore and MU_BootCoreB are the same, MU_BootCoreB is kept
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* for compatible with older platforms.
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*/
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MU_BootCoreB(base, mode);
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}
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#endif /* FSL_FEATURE_MU_NO_RSTH */
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#if !(defined(FSL_FEATURE_MU_NO_HR) && FSL_FEATURE_MU_NO_HR)
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#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR)
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/*!
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* brief Hardware reset the other core.
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*
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* This function resets the other core, the other core could mask the
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* hardware reset by calling ref MU_MaskHardwareReset. The hardware reset
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* mask feature is only available for some platforms.
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* This function could be used together with MU_BootOtherCore to control the
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* other core reset workflow.
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*
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* Example 1: Reset the other core, and no hold reset
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* code
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* MU_HardwareResetOtherCore(MU_A, true, false, bootMode);
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* endcode
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* In this example, the core at MU side B will reset with the specified boot mode.
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*
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* Example 2: Reset the other core and hold it, then boot the other core later.
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* code
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* Here the other core enters reset, and the reset is hold
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* MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare);
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* Current core boot the other core when necessary.
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* MU_BootOtherCore(MU_A, bootMode);
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* endcode
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*
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* param base MU peripheral base address.
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* param waitReset Wait the other core enters reset.
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* - true: Wait until the other core enters reset, if the other
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* core has masked the hardware reset, then this function will
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* be blocked.
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* - false: Don't wait the reset.
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* param holdReset Hold the other core reset or not.
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* - true: Hold the other core in reset, this function returns
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* directly when the other core enters reset.
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* - false: Don't hold the other core in reset, this function
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* waits until the other core out of reset.
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* param bootMode Boot mode of the other core, if p holdReset is true, this
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* parameter is useless.
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*/
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void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode)
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{
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#if (defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH)
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/* If MU does not support hold reset, then the parameter must be false. */
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assert(false == holdReset);
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#endif
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uint32_t ccr = base->CCR & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK);
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ccr |= MU_CCR_BOOT(bootMode);
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if (holdReset)
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{
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ccr |= MU_CCR_RSTH_MASK;
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}
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/* Clean the reset assert pending flag. */
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base->SR = (MU_SR_RAIP_MASK | MU_SR_RDIP_MASK);
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/* Set CCR[HR] to trigger hardware reset. */
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base->CCR = ccr | MU_CCR_HR_MASK;
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/* If wait the other core enters reset. */
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if (waitReset)
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{
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/* Wait for the other core go to reset. */
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while (0U == (base->SR & MU_SR_RAIP_MASK))
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{
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; /* Intentional empty while*/
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}
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if (!holdReset)
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{
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/* Clear CCR[HR]. */
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base->CCR = ccr;
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/* Wait for the other core out of reset. */
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while (0U == (base->SR & MU_SR_RDIP_MASK))
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{
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; /* Intentional empty while*/
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}
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}
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}
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}
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#else /* FSL_FEATURE_MU_HAS_CCR */
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/*!
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* brief Hardware reset the other core.
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*
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* This function resets the other core, the other core could mask the
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* hardware reset by calling ref MU_MaskHardwareReset. The hardware reset
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* mask feature is only available for some platforms.
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* This function could be used together with MU_BootOtherCore to control the
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* other core reset workflow.
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*
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* Example 1: Reset the other core, and no hold reset
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* code
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* MU_HardwareResetOtherCore(MU_A, true, false, bootMode);
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* endcode
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* In this example, the core at MU side B will reset with the specified boot mode.
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*
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* Example 2: Reset the other core and hold it, then boot the other core later.
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* code
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* Here the other core enters reset, and the reset is hold
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* MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare);
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* Current core boot the other core when necessary.
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* MU_BootOtherCore(MU_A, bootMode);
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* endcode
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*
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* param base MU peripheral base address.
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* param waitReset Wait the other core enters reset.
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* - true: Wait until the other core enters reset, if the other
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* core has masked the hardware reset, then this function will
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* be blocked.
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* - false: Don't wait the reset.
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* param holdReset Hold the other core reset or not.
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* - true: Hold the other core in reset, this function returns
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* directly when the other core enters reset.
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* - false: Don't hold the other core in reset, this function
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* waits until the other core out of reset.
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* param bootMode Boot mode of the other core, if p holdReset is true, this
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* parameter is useless.
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*/
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void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode)
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{
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#if (defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH)
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/* If MU does not support hold reset, then the parameter must be false. */
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||
|
|
assert(false == holdReset);
|
||
|
|
#endif
|
||
|
|
uint32_t resetFlag = 0;
|
||
|
|
|
||
|
|
uint32_t cr = base->CR & ~(MU_CR_HR_MASK | MU_CR_RSTH_MASK | MU_CR_BOOT_MASK | MU_CR_GIRn_MASK | MU_CR_NMI_MASK);
|
||
|
|
|
||
|
|
cr |= MU_CR_BOOT(bootMode);
|
||
|
|
|
||
|
|
if (holdReset)
|
||
|
|
{
|
||
|
|
cr |= MU_CR_RSTH_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
|
||
|
|
resetFlag |= MU_SR_RAIP_MASK;
|
||
|
|
#endif
|
||
|
|
#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
|
||
|
|
resetFlag |= MU_SR_RDIP_MASK;
|
||
|
|
#endif
|
||
|
|
/* Clean the reset assert pending flag. */
|
||
|
|
base->SR = resetFlag;
|
||
|
|
|
||
|
|
/* Set CR[HR] to trigger hardware reset. */
|
||
|
|
base->CR = cr | MU_CR_HR_MASK;
|
||
|
|
|
||
|
|
/* If wait the other core enters reset. */
|
||
|
|
if (waitReset)
|
||
|
|
{
|
||
|
|
#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
|
||
|
|
/* Wait for the other core go to reset. */
|
||
|
|
while (0U == (base->SR & MU_SR_RAIP_MASK))
|
||
|
|
{
|
||
|
|
; /* Intentional empty while*/
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
if (!holdReset)
|
||
|
|
{
|
||
|
|
/* Clear CR[HR]. */
|
||
|
|
base->CR = cr;
|
||
|
|
|
||
|
|
#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT)
|
||
|
|
/* Wait for the other core out of reset. */
|
||
|
|
while (0U == (base->SR & MU_SR_RDIP_MASK))
|
||
|
|
{
|
||
|
|
; /* Intentional empty while*/
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* FSL_FEATURE_MU_HAS_CCR */
|
||
|
|
#endif /* FSL_FEATURE_MU_NO_HR */
|