341 lines
12 KiB
C
341 lines
12 KiB
C
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/*
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* Copyright 2019-2021 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_mecc.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.mecc"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address to be used to gate or ungate the module clock
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*
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* @param base MECC base address
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*
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* @return The MECC instance
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*/
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static uint32_t MECC_GetInstance(MECC_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to MECC bases for each instance. */
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static MECC_Type *const s_meccBases[] = MECC_BASE_PTRS;
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t MECC_GetInstance(MECC_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_meccBases); instance++)
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{
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if (s_meccBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_meccBases));
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return instance;
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}
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/*!
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* brief MECC module initialization function.
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*
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* param base MECC base address.
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*/
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void MECC_Init(MECC_Type *base, mecc_config_t *config)
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{
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uint32_t instance = MECC_GetInstance(base);
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volatile uint64_t *ocramStartAddr = NULL;
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/* enable all the interrupt status */
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base->ERR_STAT_EN = kMECC_AllInterruptsStatusEnable;
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/* clear all the interrupt status */
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base->ERR_STATUS = kMECC_AllInterruptsFlag;
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/* disable all the interrpt */
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base->ERR_SIG_EN = 0U;
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/* enable ECC function */
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base->PIPE_ECC_EN = MECC_PIPE_ECC_EN_ECC_EN(config->enableMecc);
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__DSB();
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if (instance == (uint32_t)kMECC_Instance0)
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{
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/* Need to be initialized for ECC function operation, note that do not use memset() to initialize,
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because it will use STR instruction and STR is byte access and MECC is 64 bits access operation. */
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ocramStartAddr = (uint64_t *)config->Ocram1StartAddress;
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while (ocramStartAddr < (uint64_t *)config->Ocram1EndAddress)
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{
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*ocramStartAddr = 0x00;
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ocramStartAddr++;
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}
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}
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else if (instance == (uint32_t)kMECC_Instance1)
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{
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/* Need to be initialized for ECC function operation, note that do not use memset() to initialize,
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because it will use STR instruction and STR is byte access and MECC is 64 bits access operation. */
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ocramStartAddr = (uint64_t *)config->Ocram2StartAddress;
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while (ocramStartAddr < (uint64_t *)config->Ocram2EndAddress)
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{
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*ocramStartAddr = 0x00;
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ocramStartAddr++;
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}
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}
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else
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{
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; /* Intentional empty for MISRA rule 15.7 */
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}
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}
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/*!
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* brief Deinitializes the MECC.
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*
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*/
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void MECC_Deinit(MECC_Type *base)
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{
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/* Disable ECC function */
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base->PIPE_ECC_EN &= ~MECC_PIPE_ECC_EN_ECC_EN(1);
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}
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void MECC_GetDefaultConfig(mecc_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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/* Default MECC function. */
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config->enableMecc = false;
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/* Ocram 1 start address */
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config->Ocram1StartAddress = 0x20240000;
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/* Ocram 1 end address */
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config->Ocram1EndAddress = 0x202BFFFF;
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/* Ocram 2 address */
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config->Ocram1StartAddress = 0x202C0000;
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/* Ocram 2 address */
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config->Ocram1EndAddress = 0x2033FFFF;
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}
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/* Initialize OCRAM */
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/* Mainly use for debug, it can be deprecated when release */
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status_t MECC_ErrorInjection(
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MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber)
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{
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status_t status = kStatus_Success;
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switch (banknumber)
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{
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case kMECC_OcramBank0:
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/* Low 32 bits of Ocram bank0 error injection */
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base->ERR_DATA_INJ_LOW0 = lowerrordata;
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/* High 32 bits of Ocram bank0 error injection */
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base->ERR_DATA_INJ_HIGH0 = higherrordata;
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/* Ecc code of Ocram bank0 error injection */
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base->ERR_ECC_INJ0 = eccdata;
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break;
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case kMECC_OcramBank1:
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/* Low 32 bits of Ocram bank1 error injection */
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base->ERR_DATA_INJ_LOW1 = lowerrordata;
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/* High 32 bits of Ocram bank1 error injection */
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base->ERR_DATA_INJ_HIGH1 = higherrordata;
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/* Ecc code of Ocram bank1 error injection */
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base->ERR_ECC_INJ1 = eccdata;
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break;
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case kMECC_OcramBank2:
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/* Low 32 bits of Ocram bank2 error injection */
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base->ERR_DATA_INJ_LOW2 = lowerrordata;
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/* High 32 bits of Ocram bank2 error injection */
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base->ERR_DATA_INJ_HIGH2 = higherrordata;
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/* Ecc code of Ocram bank2 error injection */
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base->ERR_ECC_INJ2 = eccdata;
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break;
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case kMECC_OcramBank3:
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/* Low 32 bits of Ocram bank3 error injection */
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base->ERR_DATA_INJ_LOW3 = lowerrordata;
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/* High 32 bits of Ocram bank3 error injection */
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base->ERR_DATA_INJ_HIGH3 = higherrordata;
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/* Ecc code of Ocram bank3 error injection */
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base->ERR_ECC_INJ3 = eccdata;
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break;
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default:
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status = kStatus_MECC_BankMiss;
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break;
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}
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return status;
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}
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status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber)
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{
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assert(info != NULL);
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status_t status = kStatus_Success;
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uint8_t tempPosLow = 0U;
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uint8_t tempPosHigh = 0U;
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uint32_t counter = 0U;
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switch (banknumber)
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{
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case kMECC_OcramBank0:
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info->singleErrorEccCode =
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(uint8_t)((base->SINGLE_ERR_ADDR_ECC0 & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK) >>
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MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT);
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info->singleErrorAddress = (base->SINGLE_ERR_ADDR_ECC0 & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK) >>
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MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT;
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info->singleErrorDataLow = base->SINGLE_ERR_DATA_LOW0;
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info->singleErrorDataHigh = base->SINGLE_ERR_DATA_HIGH0;
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tempPosLow = (uint8_t)base->SINGLE_ERR_POS_LOW0;
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tempPosHigh = (uint8_t)base->SINGLE_ERR_POS_HIGH0;
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break;
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case kMECC_OcramBank1:
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info->singleErrorEccCode =
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(uint8_t)((base->SINGLE_ERR_ADDR_ECC1 & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK) >>
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MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT);
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info->singleErrorAddress = (base->SINGLE_ERR_ADDR_ECC1 & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK) >>
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MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT;
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info->singleErrorDataLow = base->SINGLE_ERR_DATA_LOW1;
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info->singleErrorDataHigh = base->SINGLE_ERR_DATA_HIGH1;
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tempPosLow = (uint8_t)base->SINGLE_ERR_POS_LOW1;
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tempPosHigh = (uint8_t)base->SINGLE_ERR_POS_HIGH1;
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break;
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case kMECC_OcramBank2:
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info->singleErrorEccCode =
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(uint8_t)((base->SINGLE_ERR_ADDR_ECC2 & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK) >>
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MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT);
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info->singleErrorAddress = (base->SINGLE_ERR_ADDR_ECC2 & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK) >>
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MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT;
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info->singleErrorDataLow = base->SINGLE_ERR_DATA_LOW2;
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info->singleErrorDataHigh = base->SINGLE_ERR_DATA_HIGH2;
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tempPosLow = (uint8_t)base->SINGLE_ERR_POS_LOW2;
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tempPosHigh = (uint8_t)base->SINGLE_ERR_POS_HIGH2;
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break;
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case kMECC_OcramBank3:
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info->singleErrorEccCode =
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(uint8_t)((base->SINGLE_ERR_ADDR_ECC3 & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK) >>
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MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT);
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info->singleErrorAddress = (base->SINGLE_ERR_ADDR_ECC3 & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK) >>
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MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT;
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info->singleErrorDataLow = base->SINGLE_ERR_DATA_LOW3;
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info->singleErrorDataHigh = base->SINGLE_ERR_DATA_HIGH3;
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tempPosLow = (uint8_t)base->SINGLE_ERR_POS_LOW3;
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tempPosHigh = (uint8_t)base->SINGLE_ERR_POS_HIGH3;
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break;
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default:
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status = kStatus_MECC_BankMiss;
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break;
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}
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while (tempPosLow > 0U)
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{
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tempPosLow = tempPosLow >> 1;
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counter++;
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}
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if (counter == 0U)
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{
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info->singleErrorPosLow = 0;
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}
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else
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{
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info->singleErrorPosLow = counter - 1U;
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}
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counter = 0U;
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while (tempPosHigh > 0U)
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{
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tempPosHigh = tempPosHigh >> 1;
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counter++;
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}
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if (counter == 0U)
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{
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info->singleErrorPosHigh = 0;
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}
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else
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{
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info->singleErrorPosHigh = counter - 1U;
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}
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return status;
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}
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status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber)
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{
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assert(info != NULL);
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status_t status = kStatus_Success;
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switch (banknumber)
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{
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case kMECC_OcramBank0:
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info->multiErrorEccCode =
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(uint8_t)((base->MULTI_ERR_ADDR_ECC0 & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK) >>
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MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT);
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info->multiErrorAddress = (base->MULTI_ERR_ADDR_ECC0 & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK) >>
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MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT;
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info->multiErrorDataLow = base->MULTI_ERR_DATA_LOW0;
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info->multiErrorDataHigh = base->MULTI_ERR_DATA_HIGH0;
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break;
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case kMECC_OcramBank1:
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info->multiErrorEccCode =
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(uint8_t)((base->MULTI_ERR_ADDR_ECC1 & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK) >>
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MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT);
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info->multiErrorAddress = (base->MULTI_ERR_ADDR_ECC1 & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK) >>
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MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT;
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info->multiErrorDataLow = base->MULTI_ERR_DATA_LOW1;
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info->multiErrorDataHigh = base->MULTI_ERR_DATA_HIGH1;
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break;
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case kMECC_OcramBank2:
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info->multiErrorEccCode =
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(uint8_t)((base->MULTI_ERR_ADDR_ECC2 & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK) >>
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MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT);
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info->multiErrorAddress = (base->MULTI_ERR_ADDR_ECC2 & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK) >>
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MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT;
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info->multiErrorDataLow = base->MULTI_ERR_DATA_LOW2;
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info->multiErrorDataHigh = base->MULTI_ERR_DATA_HIGH2;
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break;
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case kMECC_OcramBank3:
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info->multiErrorEccCode =
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(uint8_t)((base->MULTI_ERR_ADDR_ECC3 & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK) >>
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MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT);
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info->multiErrorAddress = (base->MULTI_ERR_ADDR_ECC3 & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK) >>
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MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT;
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info->multiErrorDataLow = base->MULTI_ERR_DATA_LOW3;
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info->multiErrorDataHigh = base->MULTI_ERR_DATA_HIGH3;
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break;
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default:
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status = kStatus_MECC_BankMiss;
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break;
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}
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|
|
|
||
|
|
return status;
|
||
|
|
}
|