388 lines
12 KiB
C
388 lines
12 KiB
C
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/*
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* File : code_run.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERsrcANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* srcange Logs:
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* Date Author Notes
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* 2018-07-05 ZYH the first version
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*/
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#include <rtthread.h>
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#define PRINTF rt_kprintf
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#include "board.h"
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#include <rthw.h>
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#include "drv_flexspi.h"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME "[FLEXSPI]"
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#define DBG_LEVEL DBG_LOG
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#define DBG_COLOR
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#include <rtdbg.h>
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#define FLEXSPI_CLOCK kCLOCK_FlexSpi
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#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
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#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 1
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#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 3
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 4
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
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#define NOR_CMD_LUT_SEQ_IDX_READID 8
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#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9
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#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
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#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12
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#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 13
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#define CUSTOM_LUT_LENGTH 60
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#define FLASH_BUSY_STATUS_POL 1
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#define FLASH_BUSY_STATUS_OFFSET 0
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static flexspi_device_config_t deviceconfig =
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{
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.flexspiRootClk = 100000000,
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.flashSize = FLASH_SIZE,
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.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
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.CSInterval = 2,
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.CSHoldTime = 3,
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.CSSetupTime = 3,
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.dataValidTime = 0,
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.columnspace = 0,
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.enableWordAddress = 0,
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.AWRSeqIndex = 0,
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.AWRSeqNumber = 0,
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.ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD,
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.ARDSeqNumber = 1,
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.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
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.AHBWriteWaitInterval = 0,
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};
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static uint32_t customLUT[CUSTOM_LUT_LENGTH] =
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{
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/* Normal read mode -SDR */
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[4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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[4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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/* Fast read mode - SDR */
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[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
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/* Fast read quad mode - SDR */
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[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x6B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(
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kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),
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/* Read extend parameters */
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[4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
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/* Write Enable */
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[4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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/* Erase Sector */
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[4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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/* Page Program - single mode */
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[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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/* Page Program - quad mode */
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[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
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[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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/* Read ID */
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[4 * NOR_CMD_LUT_SEQ_IDX_READID] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xAB, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x18),
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[4 * NOR_CMD_LUT_SEQ_IDX_READID + 1] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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/* Enable Quad mode */
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[4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),
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/* Enter QPI mode */
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[4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x38, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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/* Exit QPI mode */
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[4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xFF, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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/* Read status register */
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[4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
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/* Erase Chip */
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[4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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};
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SECTION("itcm") static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr)
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{
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flexspi_transfer_t flashXfer;
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status_t status;
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/* Write neable */
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flashXfer.deviceAddress = baseAddr;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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return status;
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}
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SECTION("itcm") static status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base)
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{
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/* Wait status ready. */
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bool isBusy;
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uint32_t readValue;
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status_t status;
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flexspi_transfer_t flashXfer;
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Read;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
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flashXfer.data = &readValue;
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flashXfer.dataSize = 1;
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do
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{
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success)
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{
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return status;
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}
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if (FLASH_BUSY_STATUS_POL)
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{
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if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
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{
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isBusy = true;
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}
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else
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{
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isBusy = false;
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}
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}
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else
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{
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if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
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{
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isBusy = false;
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}
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else
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{
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isBusy = true;
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}
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}
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}
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while (isBusy);
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return status;
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}
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SECTION("itcm") static status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base)
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{
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flexspi_transfer_t flashXfer;
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status_t status;
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uint32_t writeValue = 0x40;
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/* Write neable */
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status = flexspi_nor_write_enable(base, 0);
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if (status != kStatus_Success)
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{
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return status;
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}
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/* Enable quad mode. */
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flashXfer.deviceAddress = 0;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
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flashXfer.data = &writeValue;
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flashXfer.dataSize = 1;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success)
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{
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dbg_log(DBG_ERROR, "flexspi tranfer error\n");
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dbg_here
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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return status;
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}
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SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address)
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{
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status_t status;
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flexspi_transfer_t flashXfer;
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/* Write enable */
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success)
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{
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dbg_log(DBG_ERROR, "flexspi tranfer error\n");
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dbg_here
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return status;
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}
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Command;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success)
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{
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dbg_log(DBG_ERROR, "flexspi tranfer error\n");
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dbg_here
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
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rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
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return status;
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}
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SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src)
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{
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status_t status;
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flexspi_transfer_t flashXfer;
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/* Write neable */
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status = flexspi_nor_write_enable(base, address);
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if (status != kStatus_Success)
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{
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return status;
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}
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/* Prepare page program command */
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flashXfer.deviceAddress = address;
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flashXfer.port = kFLEXSPI_PortA1;
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flashXfer.cmdType = kFLEXSPI_Write;
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flashXfer.SeqNumber = 1;
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flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
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flashXfer.data = (uint32_t *)src;
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flashXfer.dataSize = FLASH_PAGE_SIZE;
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status = FLEXSPI_TransferBlocking(base, &flashXfer);
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if (status != kStatus_Success)
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{
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return status;
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}
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status = flexspi_nor_wait_bus_busy(base);
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|
rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
|
||
|
|
rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
SECTION("itcm") static status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId)
|
||
|
|
{
|
||
|
|
uint32_t temp;
|
||
|
|
flexspi_transfer_t flashXfer;
|
||
|
|
flashXfer.deviceAddress = 0;
|
||
|
|
flashXfer.port = kFLEXSPI_PortA1;
|
||
|
|
flashXfer.cmdType = kFLEXSPI_Read;
|
||
|
|
flashXfer.SeqNumber = 1;
|
||
|
|
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID;
|
||
|
|
flashXfer.data = &temp;
|
||
|
|
flashXfer.dataSize = 1;
|
||
|
|
|
||
|
|
status_t status = FLEXSPI_TransferBlocking(base, &flashXfer);
|
||
|
|
|
||
|
|
*vendorId = temp;
|
||
|
|
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
SECTION("itcm") int rt_hw_flexspi_init(void)
|
||
|
|
{
|
||
|
|
flexspi_config_t config;
|
||
|
|
status_t status;
|
||
|
|
uint8_t vendorID = 0;
|
||
|
|
|
||
|
|
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
|
||
|
|
rt_uint32_t level;
|
||
|
|
level = rt_hw_interrupt_disable();
|
||
|
|
CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
|
||
|
|
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24); /* Set PLL3 PFD0 clock 360MHZ. */
|
||
|
|
CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
|
||
|
|
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 120M. */
|
||
|
|
|
||
|
|
dbg_log(DBG_INFO, "NorFlash Init\r\n");
|
||
|
|
|
||
|
|
FLEXSPI_GetDefaultConfig(&config);
|
||
|
|
|
||
|
|
config.ahbConfig.enableAHBPrefetch = true;
|
||
|
|
FLEXSPI_Init(FLEXSPI, &config);
|
||
|
|
|
||
|
|
FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
|
||
|
|
|
||
|
|
FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
|
||
|
|
|
||
|
|
status = flexspi_nor_get_vendor_id(FLEXSPI, &vendorID);
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
dbg_log(DBG_INFO, "Vendor ID: 0x%x\r\n", vendorID);
|
||
|
|
|
||
|
|
status = flexspi_nor_enable_quad_mode(FLEXSPI);
|
||
|
|
if (status != kStatus_Success)
|
||
|
|
{
|
||
|
|
dbg_log(DBG_ERROR, "Entry Quad mode failed\r\n");
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
dbg_log(DBG_INFO, "NorFlash Init Done\r\n");
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return 0;
|
||
|
|
}
|