97 lines
3.3 KiB
C
97 lines
3.3 KiB
C
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#include <rtthread.h>
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#include "drv_mpu.h"
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#include "stm32f4xx_hal.h"
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/************************** PUBLIC DEFINITIONS *************************/
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/* Access permission definitions */
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#define MPU_NO_ACCESS 0x00
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#define MPU_PRIVILEGED_ACESS_USER_NO_ACCESS 0x01
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#define MPU_PRIVILEGED_RW_USER_READ_ONLY 0x02
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#define MPU_FULL_ACCESS 0x03
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#define MPU_UNPREDICTABLE 0x04
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#define MPU_PRIVILEGED_READ_ONLY_USER_NO_ACCESS 0x05
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#define MPU_READ_ONLY 0x06
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/* RASR bit definitions */
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#define MPU_RASR_REGION_SIZE(n) ((uint32_t)(n<<1))
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#define MPU_RASR_ACCESS_PERMISSION(n) ((uint32_t)(n<<24))
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void mpu_init(void)
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{
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/* Disable MPU */
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MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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/* - Region 0: 0x00000000 - 0x0007FFFF --- on-chip non-volatile memory
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* + Size: 512kB
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* + Acess permission: full access
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*/
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MPU->RNR = 0;//indicate MPU region 0
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MPU->RBAR = 0x00000000; // update the base address for the region 0
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MPU->RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS) //full access
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| MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_1MB) //512Kb size
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| MPU_REGION_ENABLE; //region enable
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/* - Region 1:0x20000000 - 0x20007FFF --- on chip SRAM
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* + Size: 32kB
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* + Access permission: full access
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*/
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MPU->RNR = 1;
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MPU->RBAR = 0x20000000; // update the base address for the region 5
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MPU->RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)
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| MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_256KB)
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| MPU_REGION_ENABLE;
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/* - Region 2: 0x40000000 - 0x400FFFFF --- APB peripheral
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* + Size: 1MB
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* + Access permission: full access
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*/
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MPU->RNR = 2;
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MPU->RBAR = 0x40000000; // update the base address for the region 2
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MPU->RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)
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| MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_128KB)
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| MPU_REGION_ENABLE;
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/* - Region 3: 0x20080000 - 0x200BFFFF --- AHB1 peripheral
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* + Size: 256KB
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* + AP=b011: full access
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*/
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MPU->RNR = 3;
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MPU->RBAR = 0x40020000; // update the base address for the region 3
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MPU->RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)
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| MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_512KB)
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| MPU_REGION_ENABLE;
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/* - Region 4: 0xE0000000 - 0xE00FFFFF --- System control
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* + Size: 1MB
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* + Access permission: full access
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*/
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MPU->RNR = 4;
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MPU->RBAR = 0xE0000000; // update the base address for the region 4
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MPU->RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)
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| MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_1MB)
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| MPU_REGION_ENABLE;
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/* - Region 5:0xA0000000 - 0xA2000000 --- external SDRAM
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* + Size: 32MB
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* + Access permission: full access
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*/
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MPU->RNR = 6;
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MPU->RBAR = 0xC0000000; // update the base address for the region 6
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MPU->RASR = MPU_RASR_ACCESS_PERMISSION(MPU_FULL_ACCESS)
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| MPU_RASR_REGION_SIZE(MPU_REGION_SIZE_32MB)
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| MPU_REGION_ENABLE;
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/* Enable the memory fault exception */
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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/* Enable MPU */
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MPU->CTRL |= MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
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}
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INIT_BOARD_EXPORT(mpu_init);
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