2020-05-26 14:49:09 +08:00
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/*
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2021-03-14 15:15:52 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2020-05-26 14:49:09 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-01-15 shelton first version
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2021-02-09 14:28:11 +08:00
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* 2021-02-09 shelton add flash macros
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2020-05-26 14:49:09 +08:00
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <at32f4xx.h>
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#include "at32_msp.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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2021-02-09 14:28:11 +08:00
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/* Just only support for AT32F40xxG */
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#define AT32_FLASH_START_ADRESS ((uint32_t)0x08000000)
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#define FLASH_PAGE_SIZE (2 * 1024)
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#define AT32_FLASH_SIZE (1024 * 1024)
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#define AT32_FLASH_END_ADDRESS ((uint32_t)(AT32_FLASH_START_ADRESS + AT32_FLASH_SIZE))
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2020-05-26 14:49:09 +08:00
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/* Internal SRAM memory size[Kbytes] <96>, Default: 96*/
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#define AT32_SRAM_SIZE 96
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#define AT32_SRAM_END (0x20000000 + AT32_SRAM_SIZE * 1024)
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2021-12-30 03:14:07 +08:00
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#if defined(__ARMCC_VERSION)
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2020-05-26 14:49:09 +08:00
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#define HEAP_END AT32_SRAM_END
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#ifdef __cplusplus
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}
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#endif
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#endif /* __BOARD_H__ */
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