248 lines
9.5 KiB
INI
248 lines
9.5 KiB
INI
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// ----------------------------------------------------------------------------
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// ATMEL Microcontroller Software Support
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// ----------------------------------------------------------------------------
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// Copyright (c) 2008, Atmel Corporation
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the disclaimer below.
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//
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// Atmel's name may not be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// File Name : at91sam9260-ek-sdram.ini
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// Object : Generic Macro File for KEIL
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// _MapRAMAt0()
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// Function description: Maps RAM at 0.
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//----------------------------------------------------------------------------
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DEFINE INT __mac_i;
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FUNC void _MapRAMAt0(){
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printf ("Changing mapping: RAM mapped to 0 \n");
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// Test and set Remap
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__mac_i = _RDWORD(0xFFFFEF00);
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if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0))
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{
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_WDWORD(0xFFFFEF00,0x03); // toggle remap bits
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}
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else
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{
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printf ("------------------------------- The Remap is done -----------------------------------\n");
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}
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}
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//----------------------------------------------------------------------------
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// _InitRSTC()
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// Function description
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// Initializes the RSTC (Reset controller).
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// This makes sense since the default is to not allow user resets, which makes it impossible to
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// apply a second RESET via J-Link
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//----------------------------------------------------------------------------
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FUNC void _InitRSTC() {
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_WDWORD(0xFFFFFD08,0xA5000001); // Allow user reset
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}
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//----------------------------------------------------------------------------
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//
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// _PllSetting()
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// Function description
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// Initializes the PMC.
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// 1. Enable the Main Oscillator
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// 2. Configure PLL
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// 3. Switch Master
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//----------------------------------------------------------------------------
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FUNC void __PllSetting()
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{
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if ((_RDWORD(0xFFFFFC30)&0x3) != 0 )
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{
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// Disable all PMC interrupt ( $$ JPP)
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// AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
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// pPmc->PMC_IDR = 0xFFFFFFFF;
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_WDWORD(0xFFFFFC64,0xFFFFFFFF);
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// AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
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_WDWORD(0xFFFFFC14,0xFFFFFFFF);
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// Disable all clock only Processor clock is enabled.
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_WDWORD(0xFFFFFC04,0xFFFFFFFE);
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// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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_WDWORD(0xFFFFFC30,0x00000001);
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_sleep_(10);
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// write reset value to PLLA and PLLB
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// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
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_WDWORD(0xFFFFFC28,0x00003F00);
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// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
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_WDWORD(0xFFFFFC2C,0x00003F00);
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_sleep_(10);
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printf ( "------------------------------- PLL Enable -----------------------------------------");
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}
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else {
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printf( " ********* Core in SLOW CLOCK mode ********* ");
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}
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}
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//----------------------------------------------------------------------------
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//
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// __PllSetting100MHz()
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// Function description
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// Set core at 200 MHz and MCK at 100 MHz
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//----------------------------------------------------------------------------
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FUNC void __PllSetting100MHz()
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{
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printf( "------------------------------- PLL Set at 100 MHz ----------------------------------");
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//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
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_WDWORD(0xFFFFFC20,0x00004001);
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_sleep_(10);
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// AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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_WDWORD(0xFFFFFC30,0x00000001);
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_sleep_(10);
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//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
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// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
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_WDWORD(0xFFFFFC28,0x2060BF09);
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_sleep_(10);
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// Configure PLLB
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_WDWORD(0xFFFFFC2C,0x207C3F0C);
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_sleep_(10);
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//* AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
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_WDWORD(0xFFFFFC30,0x00000102);
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_sleep_(10);
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}
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//----------------------------------------------------------------------------
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// __initSDRAM()
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// Function description
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// Set SDRAM for works at 100 MHz
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//----------------------------------------------------------------------------
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FUNC void __initSDRAM()
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{
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// Configure EBI Chip select
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// pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
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// AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select Assignement Register
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_WDWORD(0xFFFFEF1C,0x0001003A);
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// Configure PIOs
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// AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
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// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
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// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
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// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
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_WDWORD(0xFFFFF870,0xFFFF0000);
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_WDWORD(0xFFFFF874,0x00000000);
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_WDWORD(0xFFFFF804,0xFFFF0000);
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// psdrc->SDRAMC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |
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// AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
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// AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
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_WDWORD(0xFFFFEA08,0x85227259);
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_sleep_(10);
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// psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL
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_WDWORD(0xFFFFEA00,0x00000002);
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// *AT91C_SDRAM = 0x00000000; // Perform PRCHG
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_WDWORD(0x20000000,0x00000000);
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_sleep_(10);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+4) = 0x00000001; // Perform CBR
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_WDWORD(0x20000010,0x00000001);
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// psdrc->SDRAMC_MR = 0x00000004; // Set 2 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+8) = 0x00000002; // Perform CBR
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_WDWORD(0x20000020,0x00000002);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0xc) = 0x00000003; // Perform CBR
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_WDWORD(0x20000030,0x00000003);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x10) = 0x00000004; // Perform CBR
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_WDWORD(0x20000040,0x00000004);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x14) = 0x00000005; // Perform CBR
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_WDWORD(0x20000050,0x00000005);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x18) = 0x00000006; // Perform CBR
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_WDWORD(0x20000060,0x00000006);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x1c) = 0x00000007; // Perform CBR
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_WDWORD(0x20000070,0x00000007);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR
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_WDWORD(0xFFFFEA00,0x00000004);
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// *(AT91C_SDRAM+0x20) = 0x00000008; // Perform CBR
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_WDWORD(0x20000080,0x00000008);
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// psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
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_WDWORD(0xFFFFEA00,0x00000003);
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// *(AT91C_SDRAM+0x24) = 0xcafedede; // Perform LMR burst=1, lat=2
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_WDWORD(0x20000090,0xCAFEDEDE);
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// psdrc->SDRAMC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
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_WDWORD(0xFFFFEA04,0x000002B9);
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//* psdrc->SDRAMC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
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_WDWORD(0xFFFFEA00,0x00000000);
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//* *AT91C_SDRAM = 0x00000000; // Perform Normal mode
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_WDWORD(0x20000000,0x00000000);
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printf( "------------------------------- SDRAM Done at 100 MHz -------------------------------");
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}
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__PllSetting(); //* Init PLL
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__PllSetting100MHz();
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__initSDRAM();
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_MapRAMAt0(); //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
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_InitRSTC();
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DEBUG_CLOCK = 2000000;
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LOAD Objects\\template.axf INCREMENTAL
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PC = 0x20000000;
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//g,main
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