221 lines
11 KiB
C
221 lines
11 KiB
C
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//*****************************************************************************
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//
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// hw_ssi.h - Macros used when accessing the SSI hardware.
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//
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// Copyright (c) 2005-2009 Luminary Micro, Inc. All rights reserved.
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 4694 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_SSI_H__
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#define __HW_SSI_H__
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//*****************************************************************************
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//
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// The following are defines for the SSI register offsets.
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//
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//*****************************************************************************
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#define SSI_O_CR0 0x00000000 // Control register 0
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#define SSI_O_CR1 0x00000004 // Control register 1
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#define SSI_O_DR 0x00000008 // Data register
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#define SSI_O_SR 0x0000000C // Status register
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#define SSI_O_CPSR 0x00000010 // Clock prescale register
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#define SSI_O_IM 0x00000014 // Int mask set and clear register
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#define SSI_O_RIS 0x00000018 // Raw interrupt register
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#define SSI_O_MIS 0x0000001C // Masked interrupt register
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#define SSI_O_ICR 0x00000020 // Interrupt clear register
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#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI Control register 0.
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//
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//*****************************************************************************
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#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate.
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#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase
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#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity
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#define SSI_CR0_FRF_M 0x00000030 // Frame format mask
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#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format
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#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format
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#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format
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#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select.
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#define SSI_CR0_DSS_4 0x00000003 // 4 bit data
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#define SSI_CR0_DSS_5 0x00000004 // 5 bit data
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#define SSI_CR0_DSS_6 0x00000005 // 6 bit data
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#define SSI_CR0_DSS_7 0x00000006 // 7 bit data
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#define SSI_CR0_DSS_8 0x00000007 // 8 bit data
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#define SSI_CR0_DSS_9 0x00000008 // 9 bit data
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#define SSI_CR0_DSS_10 0x00000009 // 10 bit data
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#define SSI_CR0_DSS_11 0x0000000A // 11 bit data
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#define SSI_CR0_DSS_12 0x0000000B // 12 bit data
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#define SSI_CR0_DSS_13 0x0000000C // 13 bit data
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#define SSI_CR0_DSS_14 0x0000000D // 14 bit data
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#define SSI_CR0_DSS_15 0x0000000E // 15 bit data
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#define SSI_CR0_DSS_16 0x0000000F // 16 bit data
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#define SSI_CR0_SCR_S 8
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI Control register 1.
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//
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//*****************************************************************************
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#define SSI_CR1_EOT 0x00000010 // End of Transmission.
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#define SSI_CR1_SOD 0x00000008 // Slave mode output disable
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#define SSI_CR1_MS 0x00000004 // Master or slave mode select
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#define SSI_CR1_SSE 0x00000002 // Sync serial port enable
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#define SSI_CR1_LBM 0x00000001 // Loopback mode
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI Status register.
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//
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//*****************************************************************************
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#define SSI_SR_BSY 0x00000010 // SSI busy
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#define SSI_SR_RFF 0x00000008 // RX FIFO full
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#define SSI_SR_RNE 0x00000004 // RX FIFO not empty
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#define SSI_SR_TNF 0x00000002 // TX FIFO not full
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#define SSI_SR_TFE 0x00000001 // TX FIFO empty
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI clock prescale
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// register.
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//
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//*****************************************************************************
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#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor.
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#define SSI_CPSR_CPSDVSR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_DR register.
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//
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//*****************************************************************************
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#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data.
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#define SSI_DR_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_IM register.
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//
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//*****************************************************************************
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#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt
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// Mask.
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#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask.
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#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
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// Mask.
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#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
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// Mask.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_RIS register.
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//
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//*****************************************************************************
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#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
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// Status.
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#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
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// Status.
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#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
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// Interrupt Status.
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#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
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// Interrupt Status.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_MIS register.
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//
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//*****************************************************************************
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#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
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// Interrupt Status.
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#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
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// Interrupt Status.
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#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
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// Interrupt Status.
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#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
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// Interrupt Status.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_ICR register.
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//
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//*****************************************************************************
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#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
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// Clear.
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#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
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// Clear.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SSI_O_DMACTL register.
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//
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//*****************************************************************************
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#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable.
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#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable.
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the SSI Control
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// register 0.
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//
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//*****************************************************************************
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#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
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#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
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#define SSI_CR0_DSS 0x0000000F // Data size select
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the SSI clock
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// prescale register.
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//
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//*****************************************************************************
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#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
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//*****************************************************************************
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//
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// The following are deprecated defines for the SSI controller's FIFO size.
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//
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//*****************************************************************************
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#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
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#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the interrupt
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// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
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// registers.
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//
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//*****************************************************************************
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#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
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#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
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#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
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#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
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#endif
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#endif // __HW_SSI_H__
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