2020-11-28 18:27:24 +08:00
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/*
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2021-03-14 12:58:10 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2020-11-28 18:27:24 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-11-28 bigmagic first version
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*/
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#ifndef __DRV_I2C_H__
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#define __DRV_I2C_H__
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#include <rthw.h>
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#define BSC_C(BASE) __REG32(BASE + 0x0000) /* BSC Master Control */
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#define BSC_S(BASE) __REG32(BASE + 0x0004) /* BSC Master Status */
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#define BSC_DLEN(BASE) __REG32(BASE + 0x0008) /* BSC Master Data Length */
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#define BSC_A(BASE) __REG32(BASE + 0x000c) /* BSC Master Slave Address */
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#define BSC_FIFO(BASE) __REG32(BASE + 0x0010) /* BSC Master Data FIFO */
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#define BSC_DIV(BASE) __REG32(BASE + 0x0014) /* BSC Master Clock Divider */
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#define BSC_DEL(BASE) __REG32(BASE + 0x0018) /* BSC Master Data Delay */
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#define BSC_CLKT(BASE) __REG32(BASE + 0x001c) /* BSC Master Clock Stretch Timeout */
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/* Register masks for C Register */
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#define BSC_C_I2CEN (0x00008000) /* I2C Enable, 0 = disabled, 1 = enabled */
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#define BSC_C_INTR (0x00000400) /* Interrupt on RX */
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#define BSC_C_INTT (0x00000200) /* Interrupt on TX */
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#define BSC_C_INTD (0x00000100) /* Interrupt on DONE */
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#define BSC_C_ST (0x00000080) /* Start transfer, 1 = Start a new transfer */
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#define BSC_C_CLEAR_1 (0x00000020) /* Clear FIFO Clear */
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#define BSC_C_CLEAR_2 (0x00000010) /* Clear FIFO Clear */
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#define BSC_C_READ (0x00000001) /* Read transfer */
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/* Register masks for S Register */
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#define BSC_S_CLKT (0x00000200) /* Clock stretch timeout */
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#define BSC_S_ERR (0x00000100) /* ACK error */
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#define BSC_S_RXF (0x00000080) /* RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
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#define BSC_S_TXE (0x00000040) /* TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
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#define BSC_S_RXD (0x00000020) /* RXD FIFO contains data */
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#define BSC_S_TXD (0x00000010) /* TXD FIFO can accept data */
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#define BSC_S_RXR (0x00000008) /* RXR FIFO needs reading (full) */
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#define BSC_S_TXW (0x00000004) /* TXW FIFO needs writing (full) */
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#define BSC_S_DONE (0x00000002) /* Transfer DONE */
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#define BSC_S_TA (0x00000001) /* Transfer Active */
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#define BSC_FIFO_SIZE (16) /* BSC FIFO size */
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typedef enum
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{
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I2C_REASON_OK = 0x00, /* Success */
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I2C_REASON_ERROR_NACK = 0x01, /* Received a NACK */
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I2C_REASON_ERROR_CLKT = 0x02, /* Received Clock Stretch Timeout */
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I2C_REASON_ERROR_DATA = 0x04 /* Not all data is sent / received */
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} i2c_reason_codes;
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int rt_hw_i2c_init(void);
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#endif
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