212 lines
9.8 KiB
C
212 lines
9.8 KiB
C
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//*****************************************************************************
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//
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// am_reg_rstgen.h
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//! @file
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//!
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//! @brief Register macros for the RSTGEN module
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_REG_RSTGEN_H
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#define AM_REG_RSTGEN_H
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//*****************************************************************************
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//
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// Instance finder. (1 instance(s) available)
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//
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//*****************************************************************************
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#define AM_REG_RSTGEN_NUM_MODULES 1
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#define AM_REG_RSTGENn(n) \
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(REG_RSTGEN_BASEADDR + 0x00000000 * n)
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//*****************************************************************************
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//
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// Register offsets.
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//
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//*****************************************************************************
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#define AM_REG_RSTGEN_CFG_O 0x00000000
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#define AM_REG_RSTGEN_SWPOI_O 0x00000004
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#define AM_REG_RSTGEN_SWPOR_O 0x00000008
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#define AM_REG_RSTGEN_STAT_O 0x0000000C
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#define AM_REG_RSTGEN_CLRSTAT_O 0x00000010
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#define AM_REG_RSTGEN_TPIU_RST_O 0x00000014
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#define AM_REG_RSTGEN_INTEN_O 0x00000200
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#define AM_REG_RSTGEN_INTSTAT_O 0x00000204
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#define AM_REG_RSTGEN_INTCLR_O 0x00000208
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#define AM_REG_RSTGEN_INTSET_O 0x0000020C
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//*****************************************************************************
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//
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// RSTGEN_INTEN - Reset Interrupt register: Enable
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//
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//*****************************************************************************
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// Enables an interrupt that triggers when VCC is below BODH level.
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#define AM_REG_RSTGEN_INTEN_BODH_S 0
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#define AM_REG_RSTGEN_INTEN_BODH_M 0x00000001
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#define AM_REG_RSTGEN_INTEN_BODH(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RSTGEN_INTSTAT - Reset Interrupt register: Status
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//
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//*****************************************************************************
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// Enables an interrupt that triggers when VCC is below BODH level.
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#define AM_REG_RSTGEN_INTSTAT_BODH_S 0
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#define AM_REG_RSTGEN_INTSTAT_BODH_M 0x00000001
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#define AM_REG_RSTGEN_INTSTAT_BODH(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RSTGEN_INTCLR - Reset Interrupt register: Clear
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//
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//*****************************************************************************
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// Enables an interrupt that triggers when VCC is below BODH level.
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#define AM_REG_RSTGEN_INTCLR_BODH_S 0
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#define AM_REG_RSTGEN_INTCLR_BODH_M 0x00000001
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#define AM_REG_RSTGEN_INTCLR_BODH(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RSTGEN_INTSET - Reset Interrupt register: Set
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//
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//*****************************************************************************
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// Enables an interrupt that triggers when VCC is below BODH level.
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#define AM_REG_RSTGEN_INTSET_BODH_S 0
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#define AM_REG_RSTGEN_INTSET_BODH_M 0x00000001
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#define AM_REG_RSTGEN_INTSET_BODH(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RSTGEN_CFG - Configuration Register
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//
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//*****************************************************************************
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// Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured
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// for WDT reset.
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#define AM_REG_RSTGEN_CFG_WDREN_S 1
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#define AM_REG_RSTGEN_CFG_WDREN_M 0x00000002
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#define AM_REG_RSTGEN_CFG_WDREN(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Brown out high (2.1v) reset enable.
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#define AM_REG_RSTGEN_CFG_BODHREN_S 0
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#define AM_REG_RSTGEN_CFG_BODHREN_M 0x00000001
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#define AM_REG_RSTGEN_CFG_BODHREN(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RSTGEN_SWPOI - Software POI Reset
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//
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//*****************************************************************************
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// 0x1B generates a software POI reset.
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#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_S 0
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#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_M 0x000000FF
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#define AM_REG_RSTGEN_SWPOI_SWPOIKEY(n) (((uint32_t)(n) << 0) & 0x000000FF)
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#define AM_REG_RSTGEN_SWPOI_SWPOIKEY_KEYVALUE 0x0000001B
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//*****************************************************************************
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//
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// RSTGEN_SWPOR - Software POR Reset
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//
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//*****************************************************************************
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// 0xD4 generates a software POR reset.
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#define AM_REG_RSTGEN_SWPOR_SWPORKEY_S 0
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#define AM_REG_RSTGEN_SWPOR_SWPORKEY_M 0x000000FF
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#define AM_REG_RSTGEN_SWPOR_SWPORKEY(n) (((uint32_t)(n) << 0) & 0x000000FF)
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#define AM_REG_RSTGEN_SWPOR_SWPORKEY_KEYVALUE 0x000000D4
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//*****************************************************************************
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//
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// RSTGEN_STAT - Status Register
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//
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//*****************************************************************************
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// Reset was initiated by a Watchdog Timer Reset.
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#define AM_REG_RSTGEN_STAT_WDRSTAT_S 6
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#define AM_REG_RSTGEN_STAT_WDRSTAT_M 0x00000040
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#define AM_REG_RSTGEN_STAT_WDRSTAT(n) (((uint32_t)(n) << 6) & 0x00000040)
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// Reset was a initiated by Debugger Reset.
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#define AM_REG_RSTGEN_STAT_DBGRSTAT_S 5
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#define AM_REG_RSTGEN_STAT_DBGRSTAT_M 0x00000020
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#define AM_REG_RSTGEN_STAT_DBGRSTAT(n) (((uint32_t)(n) << 5) & 0x00000020)
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// Reset was a initiated by Software POI Reset.
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#define AM_REG_RSTGEN_STAT_POIRSTAT_S 4
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#define AM_REG_RSTGEN_STAT_POIRSTAT_M 0x00000010
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#define AM_REG_RSTGEN_STAT_POIRSTAT(n) (((uint32_t)(n) << 4) & 0x00000010)
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// Reset was a initiated by SW POR or AIRCR Reset.
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#define AM_REG_RSTGEN_STAT_SWRSTAT_S 3
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#define AM_REG_RSTGEN_STAT_SWRSTAT_M 0x00000008
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#define AM_REG_RSTGEN_STAT_SWRSTAT(n) (((uint32_t)(n) << 3) & 0x00000008)
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// Reset was initiated by a Brown-Out Reset.
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#define AM_REG_RSTGEN_STAT_BORSTAT_S 2
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#define AM_REG_RSTGEN_STAT_BORSTAT_M 0x00000004
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#define AM_REG_RSTGEN_STAT_BORSTAT(n) (((uint32_t)(n) << 2) & 0x00000004)
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// Reset was initiated by a Power-On Reset.
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#define AM_REG_RSTGEN_STAT_PORSTAT_S 1
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#define AM_REG_RSTGEN_STAT_PORSTAT_M 0x00000002
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#define AM_REG_RSTGEN_STAT_PORSTAT(n) (((uint32_t)(n) << 1) & 0x00000002)
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// Reset was initiated by an External Reset.
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#define AM_REG_RSTGEN_STAT_EXRSTAT_S 0
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#define AM_REG_RSTGEN_STAT_EXRSTAT_M 0x00000001
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#define AM_REG_RSTGEN_STAT_EXRSTAT(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RSTGEN_CLRSTAT - Clear the status register
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//
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//*****************************************************************************
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// Writing a 1 to this bit clears all bits in the RST_STAT.
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#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_S 0
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#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT_M 0x00000001
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#define AM_REG_RSTGEN_CLRSTAT_CLRSTAT(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// RSTGEN_TPIU_RST - TPIU reset
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//
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//*****************************************************************************
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// Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0'
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// to clear the reset.
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#define AM_REG_RSTGEN_TPIU_RST_TPIURST_S 0
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#define AM_REG_RSTGEN_TPIU_RST_TPIURST_M 0x00000001
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#define AM_REG_RSTGEN_TPIU_RST_TPIURST(n) (((uint32_t)(n) << 0) & 0x00000001)
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#endif // AM_REG_RSTGEN_H
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