2016-04-18 13:52:39 +08:00
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/*
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2018-10-15 01:35:07 +08:00
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* Copyright (c) 2006-2018, RT-Thread Development Team
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2016-04-18 13:52:39 +08:00
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*
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2018-10-15 01:35:07 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2016-04-18 13:52:39 +08:00
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef __MMU_H__
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#define __MMU_H__
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#include <rtthread.h>
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#define CACHE_LINE_SIZE 32
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/*
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* Hardware page table definitions.
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*
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* + Level 1 descriptor (PGD)
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* - common
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*/
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#define PGD_TYPE_MASK (3 << 0)
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#define PGD_TYPE_FAULT (0 << 0)
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#define PGD_TYPE_TABLE (1 << 0)
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#define PGD_TYPE_SECT (2 << 0)
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#define PGD_BIT4 (1 << 4)
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#define PGD_DOMAIN(x) ((x) << 5)
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#define PGD_PROTECTION (1 << 9) /* ARMv5 */
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/*
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* - section
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*/
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#define PGD_SECT_BUFFERABLE (1 << 2)
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#define PGD_SECT_CACHEABLE (1 << 3)
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#define PGD_SECT_XN (1 << 4) /* ARMv6 */
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#define PGD_SECT_AP0 (1 << 10)
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#define PGD_SECT_AP1 (1 << 11)
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#define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */
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#define PGD_SECT_APX (1 << 15) /* ARMv6 */
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#define PGD_SECT_S (1 << 16) /* ARMv6 */
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#define PGD_SECT_nG (1 << 17) /* ARMv6 */
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#define PGD_SECT_SUPER (1 << 18) /* ARMv6 */
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#define PGD_SECT_UNCACHED (0)
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#define PGD_SECT_BUFFERED (PGD_SECT_BUFFERABLE)
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#define PGD_SECT_WT (PGD_SECT_CACHEABLE)
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#define PGD_SECT_WB (PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE)
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#define PGD_SECT_MINICACHE (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE)
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#define PGD_SECT_WBWA (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE)
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#define PGD_SECT_NONSHARED_DEV (PGD_SECT_TEX(2))
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/*
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* + Level 2 descriptor (PTE)
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* - common
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*/
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#define PTE_TYPE_MASK (3 << 0)
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#define PTE_TYPE_FAULT (0 << 0)
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#define PTE_TYPE_LARGE (1 << 0)
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#define PTE_TYPE_SMALL (2 << 0)
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#define PTE_TYPE_EXT (3 << 0) /* ARMv5 */
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#define PTE_BUFFERABLE (1 << 2)
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#define PTE_CACHEABLE (1 << 3)
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/*
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* - extended small page/tiny page
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*/
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#define PTE_EXT_XN (1 << 0) /* ARMv6 */
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#define PTE_EXT_AP_MASK (3 << 4)
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#define PTE_EXT_AP0 (1 << 4)
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#define PTE_EXT_AP1 (2 << 4)
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#define PTE_EXT_AP_UNO_SRO (0 << 4)
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#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
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#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
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#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
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#define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */
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#define PTE_EXT_APX (1 << 9) /* ARMv6 */
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#define PTE_EXT_SHARED (1 << 10) /* ARMv6 */
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#define PTE_EXT_NG (1 << 11) /* ARMv6 */
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/*
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* - small page
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*/
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#define PTE_SMALL_AP_MASK (0xff << 4)
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#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
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#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
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#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
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#define PTE_SMALL_AP_URW_SRW (0xff << 4)
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/*
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* sector table properities
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*/
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#define SECT_CB (PGD_SECT_CACHEABLE|PGD_SECT_BUFFERABLE) //cache_on, write_back
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#define SECT_CNB (PGD_SECT_CACHEABLE) //cache_on, write_through
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#define SECT_NCB (PGD_SECT_BUFFERABLE) //cache_off,WR_BUF on
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#define SECT_NCNB (0 << 2) //cache_off,WR_BUF off
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#define SECT_AP_RW (PGD_SECT_AP0|PGD_SECT_AP1) //supervisor=RW, user=RW
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#define SECT_AP_RO (PGD_SECT_AP0|PGD_SECT_AP1|PGD_SECT_APX) //supervisor=RO, user=RO
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#define SECT_RWX_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read/Write/executable, cache, write back */
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#define SECT_RWX_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read/Write/executable, cache, write through */
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#define SECT_RWX_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT) /* Read/Write/executable without cache and write buffer */
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#define SECT_RWX_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT) /* Read/Write without cache and write buffer */
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#define SECT_RWNX_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write back */
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#define SECT_RWNX_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write through */
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#define SECT_RWNX_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */
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#define SECT_RWNX_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */
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#define SECT_ROX_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read Only/executable, cache, write back */
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#define SECT_ROX_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read Only/executable, cache, write through */
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#define SECT_ROX_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT) /* Read Only/executable without cache and write buffer */
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#define SECT_ROX_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT) /* Read Only without cache and write buffer */
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#define SECT_RONX_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only, cache, write back */
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#define SECT_RONX_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only, cache, write through */
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#define SECT_RONX_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only without cache and write buffer */
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#define SECT_RONX_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only without cache and write buffer */
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#define SECT_TO_PAGE (PGD_DOMAIN(0)|PGD_TYPE_TABLE) /* Level 2 descriptor (PTE) entry properity */
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/*
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* page table properities
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*/
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#define PAGE_CB (PTE_BUFFERABLE|PTE_CACHEABLE) //cache_on, write_back
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#define PAGE_CNB (PTE_CACHEABLE) //cache_on, write_through
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#define PAGE_NCB (PTE_BUFFERABLE) //cache_off,WR_BUF on
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#define PAGE_NCNB (0 << 2) //cache_off,WR_BUF off
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#define PAGE_AP_RW (PTE_EXT_AP0|PTE_EXT_AP1) //supervisor=RW, user=RW
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#define PAGE_AP_RO (PTE_EXT_AP0|PTE_EXT_AP1|PTE_EXT_APX) //supervisor=RO, user=RO
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#define PAGE_RWX_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write/executable, cache, write back */
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#define PAGE_RWX_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write/executable, cache, write through */
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#define PAGE_RWX_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write/executable without cache and write buffer */
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#define PAGE_RWX_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */
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#define PAGE_RWNX_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write, cache, write back */
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#define PAGE_RWNX_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write, cache, write through */
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#define PAGE_RWNX_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write without cache and write buffer */
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#define PAGE_RWNX_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write without cache and write buffer */
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#define PAGE_ROX_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL) /* Read Only/executable, cache, write back */
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#define PAGE_ROX_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL) /* Read Only/executable, cache, write through */
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#define PAGE_ROX_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only/executable without cache and write buffer */
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#define PAGE_ROX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */
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#define PAGE_RONX_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only, cache, write back */
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#define PAGE_RONX_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only, cache, write through */
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#define PAGE_RONX_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */
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#define PAGE_RONX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */
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#define DESC_SEC (0x2|(1<<4))
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#define CB (3<<2) //cache_on, write_back
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#define CNB (2<<2) //cache_on, write_through
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#define NCB (1<<2) //cache_off,WR_BUF on
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#define NCNB (0<<2) //cache_off,WR_BUF off
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#define AP_RW (3<<10) //supervisor=RW, user=RW
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#define AP_RO (2<<10) //supervisor=RW, user=RO
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#define DOMAIN_FAULT (0x0)
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#define DOMAIN_CHK (0x1)
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#define DOMAIN_NOTCHK (0x3)
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#define DOMAIN0 (0x0<<5)
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#define DOMAIN1 (0x1<<5)
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#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
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#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
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#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
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#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
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#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
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#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
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struct mem_desc {
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rt_uint32_t vaddr_start;
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rt_uint32_t vaddr_end;
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rt_uint32_t paddr_start;
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rt_uint32_t sect_attr; /* when page mapped */
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rt_uint32_t page_attr; /* only sector mapped valid */
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rt_uint32_t mapped_mode;
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#define SECT_MAPPED 0
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#define PAGE_MAPPED 1
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};
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void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
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#endif
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