538 lines
15 KiB
C
538 lines
15 KiB
C
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/*
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* File : drv_dma.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2015-11-19 Urey the first version
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*/
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/*********************************************************************************************************
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** ͷ<EFBFBD>ļ<EFBFBD>
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*********************************************************************************************************/
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#include <stdlib.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <dma.h>
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#include <cache.h>
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#include "board.h"
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#include "drv_clock.h"
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#include "drv_dma.h"
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#define JZDMA_DEBUG 0
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#if JZDMA_DEBUG
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#include <stdio.h>
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#define JZDMA_DBG(...) rt_kprintf(__VA_ARGS__)
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#else
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#define JZDMA_DBG(...)
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#endif
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/* ȫ<>ֱ<EFBFBD><D6B1><EFBFBD> */
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static struct jzdma_master _g_jzdma_master;
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static struct rt_dma_channel _g_rt_dma_channel[NR_DMA_CHANNELS];
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/*********************************************************************************************************
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** <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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*********************************************************************************************************/
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const static char dcm_tsz[7] = { 1, 2, 0, 0, 3, 4, 5 };
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rt_inline int _fls(int x)
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{
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__asm__("clz %0, %1" : "=r" (x) : "r" (x));
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return 32 - x;
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}
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static inline int ffs(int word)
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{
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if (!word)
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return 0;
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return _fls(word & -word);
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}
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static inline uint16_t get_max_tsz(uint32_t val, uint32_t *dcmp)
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{
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int ord;
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ord = ffs(val) - 1;
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if (ord < 0)
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ord = 0;
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else if (ord > 6)
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ord = 6;
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*dcmp &= ~DCM_TSZ_MSK;
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*dcmp |= dcm_tsz[ord] << DCM_TSZ_SHF;
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// rt_kprintf("dcmp = %x\n",*dcmp);
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/* if tsz == 8, set it to 4 */
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return ord == 3 ? 4 : 1 << ord;
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}
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static void jzdma_mcu_reset(struct jzdma_master *master)
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{
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uint32_t dmcs;
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dmcs = readl(master->base + DMCS);
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dmcs |= 0x1;
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writel(dmcs, master->base + DMCS);
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}
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static uint32_t jzdma_get_current_trans_addr(struct jzdma_channel *jz_dmac,
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uint32_t* dst_addr,
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uint32_t* src_addr,
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uint32_t direction)
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{
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uint32_t ret_val = 0;
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if (jz_dmac->status == STAT_STOPED || jz_dmac->status == STAT_PREPED)
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return 0;
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if (direction == RT_DMA_MEM_TO_DEV)
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{
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ret_val = readl(jz_dmac->iomem + CH_DSA);
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if (src_addr)
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*src_addr = ret_val;
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if (dst_addr)
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*dst_addr = readl(jz_dmac->iomem + CH_DTA);
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}
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else if (direction == RT_DMA_DEV_TO_MEM)
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{
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ret_val = readl(jz_dmac->iomem + CH_DTA);
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if (dst_addr)
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*dst_addr = ret_val;
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if (src_addr)
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*src_addr = readl(jz_dmac->iomem + CH_DSA);
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}
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else if (direction == RT_DMA_MEM_TO_MEM)
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{
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if (dst_addr)
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*dst_addr = readl(jz_dmac->iomem + CH_DTA);
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if (src_addr)
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*src_addr = readl(jz_dmac->iomem + CH_DSA);
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}
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return ret_val;
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}
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int jzdma_funcs_status(struct rt_dma_channel *dmac)
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{
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struct jzdma_channel *jz_dmac;
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RT_ASSERT(dmac != RT_NULL);
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jz_dmac = (struct jzdma_channel *)dmac->user_data;
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switch (jz_dmac->status)
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{
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case STAT_STOPED:
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return RT_DMA_STATUS_IDLE;
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break;
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default:
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break;
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}
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return RT_DMA_STATUS_BUSY;
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}
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void jzdma_funcs_reset(struct rt_dma_channel *rt_dmac)
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{
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struct jzdma_channel *jz_dmac;
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RT_ASSERT(rt_dmac != RT_NULL);
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jz_dmac = (struct jzdma_channel *)rt_dmac->user_data;
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/* <20><>ֹ<EFBFBD><D6B9>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD> */
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jz_dmac->status = STAT_STOPED;
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jz_dmac->desc_nr = 0;
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/* clear dma status */
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writel(0, jz_dmac->iomem + CH_DCS);
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD> */
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switch (rt_dmac->config.direction)
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{
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case RT_DMA_MEM_TO_DEV:
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/* MEM_TO_DEV <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DCM */
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switch(rt_dmac->config.dst_addr_width)
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{
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case RT_DMA_BUSWIDTH_1_BYTE:
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jz_dmac->desc.dcm |= DCM_SP_8 | DCM_DP_8;
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break;
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case RT_DMA_BUSWIDTH_2_BYTES:
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jz_dmac->desc.dcm |= DCM_SP_16 | DCM_DP_16;
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break;
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case RT_DMA_BUSWIDTH_4_BYTES:
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jz_dmac->desc.dcm &= ~(DCM_SP_32 | DCM_DP_32);
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break;
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default:
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JZDMA_DBG("bus width error. \r\n");
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return;
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}
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break;
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default:
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/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ <20><><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> DCM */
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switch(rt_dmac->config.src_addr_width)
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{
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case RT_DMA_BUSWIDTH_1_BYTE:
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jz_dmac->desc.dcm |= DCM_SP_8 | DCM_DP_8;
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break;
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case RT_DMA_BUSWIDTH_2_BYTES:
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jz_dmac->desc.dcm |= DCM_SP_16 | DCM_DP_16;
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break;
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case RT_DMA_BUSWIDTH_4_BYTES:
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jz_dmac->desc.dcm &= ~(DCM_SP_32 | DCM_DP_32);
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break;
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default:
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JZDMA_DBG("bus width error. \r\n");
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return;
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}
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break;
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}
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return;
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}
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rt_size_t jzdma_funcs_transfer(struct rt_dma_channel *rt_dmac , struct dma_message *message)
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{
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struct jzdma_channel *jz_dmac;
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uint32_t tsz;
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RT_ASSERT(rt_dmac != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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jz_dmac = (struct jzdma_channel *)rt_dmac->user_data;
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if(jz_dmac->status == STAT_RUNNING)
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return -RT_EBUSY;
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/* <20><><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD> */
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// writel(0, jz_dmac->iomem + CH_DCM);
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// writel(0, jz_dmac->iomem + CH_DCS);
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/* clear dma status */
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writel(0, jz_dmac->iomem + CH_DCS);
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//ˢ<><CBA2>cache
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switch(rt_dmac->config.direction)
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{
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case RT_DMA_MEM_TO_DEV:
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case RT_DMA_MEM_TO_MEM:
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rt_hw_dcache_flush_range((rt_ubase_t)(message->src_addr),message->t_size);
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break;
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default:
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break;
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}
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// /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ò<EFBFBD><C3B2><EFBFBD> */
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// switch (rt_dmac->config.direction)
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// {
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// case RT_DMA_MEM_TO_DEV:
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// /* MEM_TO_DEV <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD>ĵ<EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>DCM */
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// switch(rt_dmac->config.dst_addr_width)
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// {
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// case RT_DMA_BUSWIDTH_1_BYTE:
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// jz_dmac->desc.dcm |= DCM_SP_8 | DCM_DP_8;
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// break;
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// case RT_DMA_BUSWIDTH_2_BYTES:
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// jz_dmac->desc.dcm |= DCM_SP_16 | DCM_DP_16;
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// break;
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// case RT_DMA_BUSWIDTH_4_BYTES:
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// jz_dmac->desc.dcm &= ~(DCM_SP_32 | DCM_DP_32);
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// break;
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// default:
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// JZDMA_DBG("bus width error. \r\n");
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// return -1;
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// }
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//
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// break;
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// default:
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// /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ <20><><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> DCM */
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// switch(rt_dmac->config.src_addr_width)
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// {
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// case RT_DMA_BUSWIDTH_1_BYTE:
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// jz_dmac->desc.dcm |= DCM_SP_8 | DCM_DP_8;
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// break;
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// case RT_DMA_BUSWIDTH_2_BYTES:
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// jz_dmac->desc.dcm |= DCM_SP_16 | DCM_DP_16;
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// break;
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// case RT_DMA_BUSWIDTH_4_BYTES:
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// jz_dmac->desc.dcm &= ~(DCM_SP_32 | DCM_DP_32);
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// break;
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// default:
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// JZDMA_DBG("bus width error. \r\n");
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// return 0;
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// }
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// break;
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// }
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/* clear LINK bit when issue pending */
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jz_dmac->desc.dcm |= DCM_TIE;
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/* Disable desc link */
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jz_dmac->desc.dcm &= ~DCM_LINK;
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/* ʶ<><CAB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD> */
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switch(message->src_option)
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{
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case RT_DMA_ADDR_INC:
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jz_dmac->desc.dcm |= DCM_SAI;
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break;
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case RT_DMA_ADDR_FIX:
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jz_dmac->desc.dcm &= ~DCM_SAI;
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break;
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default:
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return -RT_EIO;
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}
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switch(message->dst_option)
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{
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case RT_DMA_ADDR_INC:
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jz_dmac->desc.dcm |= DCM_DAI;
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break;
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case RT_DMA_ADDR_FIX:
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jz_dmac->desc.dcm &= ~DCM_DAI;
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break;
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default:
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return -RT_EIO;
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}
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/* <20><><EFBFBD><EFBFBD>TSZ */
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if(rt_dmac->ch == 1)
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{
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/*
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* for special channel1 tsz = 7 (auto)
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*/
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jz_dmac->desc.dcm |= 7 << 8;
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tsz = message->t_size;
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}
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else
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{
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if(rt_dmac->config.direction == RT_DMA_MEM_TO_DEV)
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{
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tsz = get_max_tsz((uint32_t)(message->src_addr) | message->t_size | rt_dmac->config.dst_maxburst, &jz_dmac->desc.dcm);
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tsz = message->t_size / tsz;
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}
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|
else
|
|||
|
|
{
|
|||
|
|
tsz = get_max_tsz((uint32_t)(message->dst_addr) | message->t_size | rt_dmac->config.src_maxburst, &jz_dmac->desc.dcm);
|
|||
|
|
tsz = message->t_size / tsz;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
jz_dmac->desc.dsa = (uint32_t)(message->src_addr) & 0x1FFFFFFF;
|
|||
|
|
JZDMA_DBG("dsa = %x\n",jz_dmac->desc.dsa);
|
|||
|
|
jz_dmac->desc.dta = (uint32_t)(message->dst_addr) & 0x1FFFFFFF;
|
|||
|
|
JZDMA_DBG("dta = %x\n",jz_dmac->desc.dta);
|
|||
|
|
jz_dmac->desc.dtc = tsz;
|
|||
|
|
JZDMA_DBG("dtc = %x\n",jz_dmac->desc.dtc);
|
|||
|
|
// jz_dmac->desc.drt = jz_dmac->type;
|
|||
|
|
jz_dmac->desc.drt = (uint32_t)message->t_mode;
|
|||
|
|
JZDMA_DBG("drt = %x\n",jz_dmac->desc.drt);
|
|||
|
|
jz_dmac->desc.sd = 0;
|
|||
|
|
JZDMA_DBG("dcm = %x\n",jz_dmac->desc.dcm);
|
|||
|
|
|
|||
|
|
/* I don't want to use 8-word descriptors */
|
|||
|
|
writel(DCS_NDES,jz_dmac->iomem + CH_DCS);
|
|||
|
|
|
|||
|
|
/* Update DMA Channel Register */
|
|||
|
|
writel(jz_dmac->desc.dsa, jz_dmac->iomem + CH_DSA);
|
|||
|
|
writel(jz_dmac->desc.dta, jz_dmac->iomem + CH_DTA);
|
|||
|
|
writel(jz_dmac->desc.dtc, jz_dmac->iomem + CH_DTC);
|
|||
|
|
writel(jz_dmac->desc.drt, jz_dmac->iomem + CH_DRT);
|
|||
|
|
|
|||
|
|
jz_dmac->status = STAT_RUNNING;
|
|||
|
|
jz_dmac->desc.dcm &= ~DCM_LINK;
|
|||
|
|
jz_dmac->desc.dcm |= DCM_TIE;
|
|||
|
|
writel(jz_dmac->desc.dcm, jz_dmac->iomem + CH_DCM);
|
|||
|
|
|
|||
|
|
/* DCS.CTE = 1 */
|
|||
|
|
writel(readl(jz_dmac->iomem + CH_DCS) | DCS_CTE,(jz_dmac->iomem + CH_DCS));
|
|||
|
|
|
|||
|
|
return message->t_size;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
static void jzdma_int_handler(int vector,void *param)
|
|||
|
|
{
|
|||
|
|
struct jzdma_master *master = &_g_jzdma_master;
|
|||
|
|
uint32_t pending,dcs;
|
|||
|
|
int i;
|
|||
|
|
|
|||
|
|
pending = readl(master->base + DIRQP);
|
|||
|
|
|
|||
|
|
for (i = 0; i < NR_DMA_CHANNELS; i++)
|
|||
|
|
{
|
|||
|
|
struct rt_dma_channel *rt_dmac = &_g_rt_dma_channel[i];
|
|||
|
|
struct jzdma_channel *jz_dmac = (struct jzdma_channel *)rt_dmac->user_data;
|
|||
|
|
|
|||
|
|
if (!(pending & (1 << i)))
|
|||
|
|
continue;
|
|||
|
|
|
|||
|
|
dcs = readl(jz_dmac->iomem + CH_DCS);
|
|||
|
|
jz_dmac->dcs_saved = dcs;
|
|||
|
|
|
|||
|
|
writel(0, jz_dmac->iomem + CH_DCS);
|
|||
|
|
if (jz_dmac->status != STAT_RUNNING)
|
|||
|
|
continue;
|
|||
|
|
|
|||
|
|
/* Address Error. */
|
|||
|
|
if(dcs & DCS_AR)
|
|||
|
|
{
|
|||
|
|
JZDMA_DBG("Addr Error: DCS%d=%lx\n",i,dcs);
|
|||
|
|
|
|||
|
|
rt_dma_contex_service(rt_dmac,RT_DMA_EVENT_ERROR);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* DMA halt */
|
|||
|
|
if (dcs & DCS_HLT)
|
|||
|
|
{
|
|||
|
|
JZDMA_DBG("DMA Halt: DCS%d=%lx\n", i, dcs);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* DMA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
|
|||
|
|
if (dcs & DCS_TT)
|
|||
|
|
{
|
|||
|
|
jz_dmac->status = STAT_STOPED;
|
|||
|
|
JZDMA_DBG("DMA CH%d Over\n",i);
|
|||
|
|
|
|||
|
|
//ˢ<><CBA2>cache
|
|||
|
|
switch(rt_dmac->config.direction)
|
|||
|
|
{
|
|||
|
|
case RT_DMA_DEV_TO_MEM:
|
|||
|
|
case RT_DMA_MEM_TO_MEM:
|
|||
|
|
{
|
|||
|
|
struct dma_message *message;
|
|||
|
|
message = rt_dma_get_current_message(rt_dmac);
|
|||
|
|
if(message)
|
|||
|
|
{
|
|||
|
|
// r4k_dcache_inv((rt_ubase_t)(message->dst_addr),message->t_size);
|
|||
|
|
rt_hw_dcache_invalidate_range((rt_ubase_t)(message->dst_addr),message->t_size);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
default:
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
rt_dma_contex_service(rt_dmac,RT_DMA_EVENT_COMPLETE);
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
pending = readl(master->base + DMAC);
|
|||
|
|
pending &= ~(DMAC_HLT | DMAC_AR);
|
|||
|
|
writel(pending, master->base + DMAC);
|
|||
|
|
writel(0, master->base + DIRQP);
|
|||
|
|
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* not use */
|
|||
|
|
static void jzdma_link_int_handler(int irq, void *param)
|
|||
|
|
{
|
|||
|
|
struct jzdma_master *master = &_g_jzdma_master;
|
|||
|
|
uint32_t pending;
|
|||
|
|
int i;
|
|||
|
|
|
|||
|
|
pending = readl(master->base + DESIRQP);
|
|||
|
|
|
|||
|
|
JZDMA_DBG("Link INT \n");
|
|||
|
|
|
|||
|
|
for (i = 0; i < NR_DMA_CHANNELS; i++)
|
|||
|
|
{
|
|||
|
|
struct rt_dma_channel *rt_dmac = &_g_rt_dma_channel[i];
|
|||
|
|
struct jzdma_channel *jz_dmac = (struct jzdma_channel *)rt_dmac->user_data;
|
|||
|
|
|
|||
|
|
if (!(pending & (1 << i)))
|
|||
|
|
continue;
|
|||
|
|
if (jz_dmac->status != STAT_RUNNING)
|
|||
|
|
continue;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
writel((readl(master->base + DIC)&(~pending)),master->base + DIC);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* RTDMA <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> <20>ӿ<EFBFBD>*/
|
|||
|
|
struct dma_ops _g_jzdma_ops =
|
|||
|
|
{
|
|||
|
|
.reset = jzdma_funcs_reset,
|
|||
|
|
.trans = jzdma_funcs_transfer,
|
|||
|
|
.status = jzdma_funcs_status
|
|||
|
|
};
|
|||
|
|
|
|||
|
|
|
|||
|
|
int rt_hw_jzdma_init(void)
|
|||
|
|
{
|
|||
|
|
int i;
|
|||
|
|
struct jzdma_master *master = &_g_jzdma_master;
|
|||
|
|
uint32_t pdma_program = 0;
|
|||
|
|
/* ʹ<><CAB9>DMA ʱ<><CAB1> */
|
|||
|
|
master->clk = clk_get("pdma");
|
|||
|
|
clk_enable(master->clk);
|
|||
|
|
|
|||
|
|
master->base = DMAC_BASE;
|
|||
|
|
master->irq = IRQ_PDMA;
|
|||
|
|
master->irq_pdmad = IRQ_PDMAD;
|
|||
|
|
|
|||
|
|
/* ???
|
|||
|
|
* indeed it think we should also enable special channel<0,1>
|
|||
|
|
* but when you guys enable it (set bit1) the main cpu will never get interrupt from dma channel when TC count down to 0
|
|||
|
|
*/
|
|||
|
|
writel(1 | (0x3f << 16), master->base + DMAC);
|
|||
|
|
|
|||
|
|
for (i = 0; i < NR_DMA_CHANNELS; i++)
|
|||
|
|
{
|
|||
|
|
struct rt_dma_channel *rt_dmac = &(_g_rt_dma_channel[i]);
|
|||
|
|
struct jzdma_channel *jz_dmac = &(master->channel[i]);
|
|||
|
|
struct dma_config config =
|
|||
|
|
{
|
|||
|
|
.direction = RT_DMA_MEM_TO_MEM,
|
|||
|
|
.src_addr_width = RT_DMA_BUSWIDTH_4_BYTES,
|
|||
|
|
.src_maxburst = (64 * 1024),
|
|||
|
|
.dst_addr_width = RT_DMA_BUSWIDTH_4_BYTES,
|
|||
|
|
.dst_maxburst = (64 * 1024),
|
|||
|
|
};
|
|||
|
|
|
|||
|
|
rt_dmac->ch = i;
|
|||
|
|
|
|||
|
|
jz_dmac->type = JZDMA_REQ_AUTO;
|
|||
|
|
jz_dmac->iomem = master->base + i * 0x20;
|
|||
|
|
jz_dmac->status = STAT_STOPED;
|
|||
|
|
jz_dmac->dcm_def = 0;
|
|||
|
|
|
|||
|
|
pdma_program |= (0x01 << i);
|
|||
|
|
|
|||
|
|
rt_dma_drv_install(rt_dmac,&_g_jzdma_ops,&config,jz_dmac);
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* the corresponding dma channel is set programmable */
|
|||
|
|
// writel(pdma_program, dma->base + DMACP);
|
|||
|
|
|
|||
|
|
jzdma_mcu_reset(master);
|
|||
|
|
|
|||
|
|
/* ע<><D7A2> DMA<4D>ж<EFBFBD> */
|
|||
|
|
rt_hw_interrupt_install(IRQ_PDMA,jzdma_int_handler,RT_NULL,"PDMA");
|
|||
|
|
rt_hw_interrupt_umask(IRQ_PDMA);
|
|||
|
|
|
|||
|
|
rt_hw_interrupt_install(IRQ_PDMAD,jzdma_link_int_handler,RT_NULL,"PDMAD");
|
|||
|
|
rt_hw_interrupt_umask(IRQ_PDMAD);
|
|||
|
|
|
|||
|
|
return RT_EOK;
|
|||
|
|
}
|
|||
|
|
INIT_DEVICE_EXPORT(rt_hw_jzdma_init);
|