400 lines
14 KiB
C
400 lines
14 KiB
C
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/**
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*********************************************************************************
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*
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* @file ald_i2s.c
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* @brief Header file of I2S module driver.
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*
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* @version V1.0
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* @date 09 Mar. 2023
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* @author AE Team
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* @note
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* Change Logs:
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* Date Author Notes
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* 09 Mar. 2023 Lisq The first version
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*
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* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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**********************************************************************************
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*/
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#ifndef __ALD_I2S_H__
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#define __ALD_I2S_H__
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#include "ald_utils.h"
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#include "ald_dma.h"
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/** @addtogroup ES32VF2264_ALD
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* @{
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*/
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/** @addtogroup I2S
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* @{
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*/
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/** @defgroup I2S_Public_Types I2S Public Types
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* @{
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*/
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/**
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* @brief Channel length
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*/
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typedef enum {
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ALD_I2S_WIDE_16 = 0x0U, /**< Channel length is 16 */
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ALD_I2S_WIDE_32 = 0x1U, /**< Channel length is 32 */
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} ald_i2s_chlen_t;
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/**
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* @brief Data length
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*/
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typedef enum {
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ALD_I2S_LEN_16 = 0x0U, /**< Data length is 16 */
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ALD_I2S_LEN_24 = 0x1U, /**< Data length is 24 */
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ALD_I2S_LEN_32 = 0x2U, /**< Data length is 32 */
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} ald_i2s_datalen_t;
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/**
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* @brief Inactive state clock polarity
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*/
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typedef enum {
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ALD_I2S_INACTIVE_LOW = 0x0U, /**< Inactive state is low */
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ALD_I2S_INACTIVE_HIGH = 0x1U, /**< Inactive state is high */
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} ald_i2s_cpol_t;
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/**
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* @brief I2s standard
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*/
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typedef enum {
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ALD_I2S_STD_PHI = 0x0U, /**< Philips standard */
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ALD_I2S_STD_MSB = 0x1U, /**< MSB standard */
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ALD_I2S_STD_LSB = 0x2U, /**< LSB standard */
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ALD_I2S_STD_PCM = 0x3U, /**< PCM standard */
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} ald_i2s_standard_t;
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/**
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* @brief I2s configuration mode
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*/
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typedef enum {
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ALD_I2S_SLAVE_DUPLEX = 0x0U, /**< I2S slave full duplex mode */
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ALD_I2S_SLAVE_RECEIVE = 0x1U, /**< I2S slave receive mode */
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ALD_I2S_SLAVE_TRANSMIT = 0x2U, /**< I2S slave transmit mode */
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ALD_I2S_MASTER_DUPLEX = 0x4U, /**< I2S master full duplex mode */
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ALD_I2S_MASTER_TRANSMIT = 0x5U, /**< I2S master transmit mode */
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ALD_I2S_MASTER_RECEIVE = 0x6U, /**< I2S master receive mode */
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} ald_i2s_cfg_t;
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/**
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* @brief Pcm frame synchronization
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*/
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typedef enum {
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ALD_I2S_FRAME_SHORT = 0x0U, /**< I2S PCM short frame */
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ALD_I2S_FRAME_LONG = 0x1U, /**< I2S PCM long frame */
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} ald_i2s_pcms_t;
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/**
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* @brief Channel side
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*/
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typedef enum {
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ALD_I2S_SIDE_LEFT = 0U, /**< Sound channel is left */
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ALD_I2S_SIDE_RIGHT = 1U, /**< Sound channel is right */
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} ald_i2s_ch_side_t;
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/**
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* @brief I2S error status
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*/
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typedef enum {
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ALD_I2S_ERROR_NONE = 0x0U, /**< none */
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ALD_I2S_ERROR_MODF = 0x1U, /**< mode fault */
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ALD_I2S_ERROR_DMA = 0x2U, /**< crc error */
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ALD_I2S_ERROR_FRE = 0x4U, /**< frame error */
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ALD_I2S_ERROR_RXOV = 0x8U, /**< receive over error */
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ALD_I2S_ERROR_TXOV = 0x10U, /**< dma error */
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ALD_I2S_ERROR_FLAG = 0x20U, /**< interrupt flag error */
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} ald_i2s_error_t;
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/**
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* @brief interrupt control
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*/
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typedef enum {
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ALD_I2S_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */
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ALD_I2S_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */
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ALD_I2S_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */
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ALD_I2S_IT_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt */
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ALD_I2S_IT_RXNE = (1U << 8), /**< Receive fifo not empty interrupt */
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ALD_I2S_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */
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ALD_I2S_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */
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ALD_I2S_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */
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ALD_I2S_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */
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ALD_I2S_IT_CRCERR = (1U << 16), /**< Crc error interrupt */
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ALD_I2S_IT_MODF = (1U << 17), /**< Mode error interrupt */
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ALD_I2S_IT_FRE = (1U << 18), /**< Frame error interrupt */
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} ald_i2s_it_t;
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/**
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* @brief I2S dma request definition
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*/
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typedef enum {
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ALD_I2S_DMA_REQ_TX = 0U, /**< TX dma request */
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ALD_I2S_DMA_REQ_RX = 1U, /**< RX dma request */
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} ald_i2s_dma_req_t;
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/**
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* @brief interrupt flag
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*/
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typedef enum {
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ALD_I2S_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */
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ALD_I2S_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */
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ALD_I2S_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */
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ALD_I2S_IF_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt flag */
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ALD_I2S_IF_RXNE = (1U << 8), /**< Receive fifo not empty interrupt flag */
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ALD_I2S_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */
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ALD_I2S_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */
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ALD_I2S_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */
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ALD_I2S_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */
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ALD_I2S_IF_CRCERR = (1U << 16), /**< Crc error interrupt flag */
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ALD_I2S_IF_MODF = (1U << 17), /**< Mode error interrupt flag */
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ALD_I2S_IF_FRE = (1U << 18), /**< Frame error interrupt flag */
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} ald_i2s_flag_t;
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/**
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* @brief I2S state structures definition
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*/
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typedef enum {
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ALD_I2S_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
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ALD_I2S_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
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ALD_I2S_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
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ALD_I2S_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */
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ALD_I2S_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */
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ALD_I2S_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */
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ALD_I2S_STATE_TIMEOUT = 0x03U, /**< Timeout state */
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ALD_I2S_STATE_ERROR = 0x04U, /**< Error */
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} ald_i2s_state_t;
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/**
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* @brief I2S status definition
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*/
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typedef enum {
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ALD_I2S_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */
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ALD_I2S_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */
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ALD_I2S_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */
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ALD_I2S_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */
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ALD_I2S_STATUS_TXTH = (1U << 4), /**< Transmit fifo under threshold status */
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ALD_I2S_STATUS_RXNE = (1U << 8), /**< Receive fifo not empty status */
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ALD_I2S_STATUS_RXF = (1U << 9), /**< Receive fifo full status */
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ALD_I2S_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */
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ALD_I2S_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */
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ALD_I2S_STATUS_RXTH = (1U << 12), /**< Receive fifo over threshold status */
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ALD_I2S_STATUS_CHSIDE = (1U << 14), /**< Sound channel status */
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ALD_I2S_STATUS_BUSY = (1U << 15), /**< BUSY status */
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} ald_i2s_status_t;
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/**
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* @brief I2S TXE/RXNE status definition
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*/
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typedef enum {
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ALD_I2S_SR_TXE = 0U, /**< STAT TXE set */
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ALD_I2S_SR_RXNE = 1U, /**< STAT RXTH set */
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ALD_I2S_SR_TXE_RXNE = 2U, /**< STAT TXE and RXTH set */
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} ald_i2s_sr_status_t;
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/**
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* @brief I2S init structure definition
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*/
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typedef struct {
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ald_i2s_chlen_t ch_len; /**< Channel length choose */
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ald_i2s_datalen_t data_len; /**< Data length choose */
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ald_i2s_cpol_t polarity; /**< Inactive clock polarity */
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ald_i2s_standard_t standard; /**< Standard choose */
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ald_i2s_pcms_t pcm_frame; /**< PCM frame synchronization */
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type_func_t ext_clk_en; /**< Choose external clock or APB1 clock */
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uint32_t ext_clk; /**< External clock, unit is Hz */
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type_func_t mck_en; /**< Main clock output function */
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uint32_t sampling; /**< Sampling rate. eg. 192*1024-192KHz, 96*1024-96KHz */
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} ald_i2s_init_t;
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/**
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* @brief I2S handle structure definition
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*/
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typedef struct ald_i2s_handle_s {
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SPI_I2S_TypeDef *perh; /**< I2S registers base address */
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ald_i2s_init_t init; /**< I2S communication parameters */
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uint16_t *tx_buf; /**< Pointer to I2S Tx transfer buffer */
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uint32_t tx_size; /**< I2S Tx transfer size */
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uint32_t tx_count; /**< I2S Tx transfer counter */
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uint16_t *rx_buf; /**< Pointer to I2S Rx transfer buffer */
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uint32_t rx_size; /**< I2S Rx Transfer size */
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uint32_t rx_count; /**< I2S Rx Transfer Counter */
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ald_dma_handle_t hdmatx; /**< I2S DMA handle parameters */
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ald_dma_handle_t hdmarx; /**< I2S DMA handle parameters */
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lock_state_t lock; /**< Locking object */
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ald_i2s_state_t state; /**< I2S communication state */
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uint8_t side; /**< I2S channel side */
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uint32_t err_code; /**< I2S error code */
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void (*tx_cplt_cbk)(struct ald_i2s_handle_s *arg); /**< Tx completed callback */
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void (*rx_cplt_cbk)(struct ald_i2s_handle_s *arg); /**< Rx completed callback */
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void (*err_cbk)(struct ald_i2s_handle_s *arg); /**< error callback */
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} ald_i2s_handle_t;
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/**
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* @}
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*/
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/** @defgroup I2S_Public_Macros I2S Public Macros
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* @{
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*/
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#define ALD_I2S_RESET_HANDLE_STATE(x) ((x)->state = ALD_I2S_STATE_RESET)
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#define ALD_I2S_ENABLE(x) (SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))
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#define ALD_I2S_DISABLE(x) (CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))
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/**
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* @}
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*/
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/** @defgroup I2S_Private_Macros I2S Private Macros
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* @{
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*/
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#define IS_I2S(x) ((x) == I2S0)
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#define IS_I2S_CH_LEN(x) (((x) == ALD_I2S_WIDE_16) || \
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((x) == ALD_I2S_WIDE_32))
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#define IS_I2S_DATE_LEN(x) (((x) == ALD_I2S_LEN_16) || \
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((x) == ALD_I2S_LEN_24) || \
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((x) == ALD_I2S_LEN_32))
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#define IS_I2S_CPOL(x) (((x) == ALD_I2S_INACTIVE_LOW) || \
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((x) == ALD_I2S_INACTIVE_HIGH))
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#define IS_I2S_STANDARD(x) (((x) == ALD_I2S_STD_PHI) || \
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((x) == ALD_I2S_STD_MSB) || \
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((x) == ALD_I2S_STD_LSB) || \
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((x) == ALD_I2S_STD_PCM))
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#define IS_I2S_PCMS(x) (((x) == ALD_I2S_FRAME_SHORT) || \
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((x) == ALD_I2S_FRAME_LONG))
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#define IS_I2S_IT(x) (((x) == ALD_I2S_IT_TXE) || \
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((x) == ALD_I2S_IT_TXOV) || \
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((x) == ALD_I2S_IT_TXUD) || \
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((x) == ALD_I2S_IT_TXTH) || \
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((x) == ALD_I2S_IT_RXNE) || \
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((x) == ALD_I2S_IT_RXF) || \
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((x) == ALD_I2S_IT_RXOV) || \
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((x) == ALD_I2S_IT_RXUD) || \
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((x) == ALD_I2S_IT_RXTH) || \
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((x) == ALD_I2S_IT_CRCERR) || \
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((x) == ALD_I2S_IT_MODF) || \
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((x) == ALD_I2S_IT_FRE))
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#define IS_I2S_IF(x) (((x) == ALD_I2S_IF_TXE) || \
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((x) == ALD_I2S_IF_TXOV) || \
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((x) == ALD_I2S_IF_TXUD) || \
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((x) == ALD_I2S_IF_TXTH) || \
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((x) == ALD_I2S_IF_RXNE) || \
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((x) == ALD_I2S_IF_RXF) || \
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((x) == ALD_I2S_IF_RXOV) || \
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||
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((x) == ALD_I2S_IF_RXUD) || \
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||
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((x) == ALD_I2S_IF_RXTH) || \
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||
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((x) == ALD_I2S_IF_CRCERR) || \
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||
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((x) == ALD_I2S_IF_MODF) || \
|
||
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((x) == ALD_I2S_IF_FRE))
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||
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#define IS_I2S_STATUS(x) (((x) == ALD_I2S_STATUS_TXE) || \
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||
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((x) == ALD_I2S_STATUS_TXF) || \
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||
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((x) == ALD_I2S_STATUS_TXOV) || \
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||
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((x) == ALD_I2S_STATUS_TXUD) || \
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||
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((x) == ALD_I2S_STATUS_TXTH) || \
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||
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((x) == ALD_I2S_STATUS_RXNE) || \
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||
|
|
((x) == ALD_I2S_STATUS_RXF) || \
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||
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|
((x) == ALD_I2S_STATUS_RXOV) || \
|
||
|
|
((x) == ALD_I2S_STATUS_RXUD) || \
|
||
|
|
((x) == ALD_I2S_STATUS_RXTH) || \
|
||
|
|
((x) == ALD_I2S_STATUS_CHSIDE) || \
|
||
|
|
((x) == ALD_I2S_STATUS_BUSY))
|
||
|
|
#define IS_I2S_DMA_REQ(x) (((x) == ALD_I2S_DMA_REQ_TX) || \
|
||
|
|
((x) == ALD_I2S_DMA_REQ_RX))
|
||
|
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/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup I2S_Public_Functions
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup I2S_Public_Functions_Group1
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
ald_status_t ald_i2s_init(ald_i2s_handle_t *hperh);
|
||
|
|
void ald_i2s_reset(ald_i2s_handle_t *hperh);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup I2S_Public_Functions_Group2
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
ald_status_t ald_i2s_master_send(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout);
|
||
|
|
ald_status_t ald_i2s_master_recv(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout);
|
||
|
|
ald_status_t ald_i2s_master_send_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size);
|
||
|
|
ald_status_t ald_i2s_master_recv_by_it(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size);
|
||
|
|
|
||
|
|
ald_status_t ald_i2s_master_send_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel);
|
||
|
|
ald_status_t ald_i2s_master_recv_by_dma(ald_i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch);
|
||
|
|
ald_status_t ald_i2s_dma_pause(ald_i2s_handle_t *hperh);
|
||
|
|
ald_status_t ald_i2s_dma_resume(ald_i2s_handle_t *hperh);
|
||
|
|
ald_status_t ald_i2s_dma_stop(ald_i2s_handle_t *hperh);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup I2S_Public_Functions_Group3
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
void ald_i2s_irq_handler(ald_i2s_handle_t *hperh);
|
||
|
|
void ald_i2s_interrupt_config(ald_i2s_handle_t *hperh, ald_i2s_it_t it, type_func_t state);
|
||
|
|
void ald_i2s_dma_req_config(ald_i2s_handle_t *hperh, ald_i2s_dma_req_t req, type_func_t state);
|
||
|
|
flag_status_t ald_i2s_get_status(ald_i2s_handle_t *hperh, ald_i2s_status_t status);
|
||
|
|
it_status_t ald_i2s_get_it_status(ald_i2s_handle_t *hperh, ald_i2s_it_t it);
|
||
|
|
flag_status_t ald_i2s_get_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag);
|
||
|
|
flag_status_t ald_i2s_get_mask_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag);
|
||
|
|
void ald_i2s_clear_flag_status(ald_i2s_handle_t *hperh, ald_i2s_flag_t flag);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/** @addtogroup I2S_Public_Functions_Group4
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
ald_i2s_state_t ald_i2s_get_state(ald_i2s_handle_t *hperh);
|
||
|
|
uint32_t ald_i2s_get_error(ald_i2s_handle_t *hperh);
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif /* __cplusplus */
|
||
|
|
#endif /* __ALD_I2S_H__ */
|